Nexperia USA Inc. HEF4104BT,652

Overview

HEF4104BT,652 from Nexperia is a quad low-to-high voltage translator IC with complementary 3-state outputs (B_n and B̅_n), designed for bidirectional level shifting between two independent supply domains (VDD(A) = 3–15 V, VDD(B) = VDD(A) to 15 V). It supports 5 V/10 V/15 V parametric ratings, features input clamp diodes enabling overvoltage-tolerant interfacing, and operates across -40 °C to +85 °C for industrial control and mixed-voltage logic interfacing.

For engineers reviewing the HEF4104BT,652 datasheet, HEF4104BT,652 pinout, HEF4104BT,652 application, or HEF4104BT,652 equivalent, this device is selected for precise dual-rail translation where output enable control, high noise immunity, symmetrical output drive, and JEDEC JESD13-B compliance are required in legacy CMOS and mixed-supply systems.

Technical Context

The HEF4104BT,652 implements four independent level-shifting channels, each with separate A-side inputs (A0–A3) and complementary B-side outputs (B_n/B̅_n) referenced to distinct supply rails VDD(A) and VDD(B). Its functional table confirms that OE = LOW forces all outputs into high-impedance OFF-state, while OE = HIGH enables translation with propagation delays as low as 57 ns (VDD = 15 V).

Input clamping diodes allow safe interface to voltages exceeding VDD(A), supporting current-limiting resistor-based overvoltage protection. Static characteristics include VIH = 11.0 V (at VDD(A) = 15 V), VOL = 0.05 V (|IOL| < 1 μA), and IOZ = ±12.0 μA at 15 V, ensuring robust off-state isolation and rail-to-rail output swing capability.

Key Specifications

Pinout & Package

HEF4104BT,652 is housed in a plastic small outline package (SO16), SOT109-1, with 16 leads and 3.9 mm body width. Pin 1 is marked by a bevelled corner or index notch per JEDEC MS-012.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad low-to-high voltage translation applications.

Compared with SN74LVC4245APWR and TXS0104EPRJR, the HEF4104BT,652 uniquely supports 15 V operation, offers complementary outputs per channel, includes input clamp diodes for overvoltage resilience, and provides explicit OE control-making it irreplaceable in industrial 5 V/10 V/15 V mixed-rail systems requiring deterministic unidirectional translation and robust ESD performance.

Availability

HEF4104BT,652 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, mixed-voltage microcontroller interface, legacy system bus bridging, and automated test equipment signal conditioning requiring stable component supply across extended temperature ranges and dual-rail voltage translation.

Supply support for HEF4104BT,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, high-reliability standard logic, analog, and discrete components, with manufacturing rooted in process technology leadership and automotive-grade quality systems.

The HEF4104BT,652 belongs to Nexperia's legacy CMOS logic portfolio, engineered specifically for industrial-level voltage translation in mixed-supply systems where reliability, wide operating range, and JEDEC compliance are mandatory.

FAQ

Can HEF4104BT,652 translate from a higher voltage domain to a lower one (e.g., 15 V → 5 V)?

No - the HEF4104BT,652 is strictly a low-to-high voltage translator: A-side inputs must be referenced to VDD(A), and B-side outputs to VDD(B), where VDD(B) ≥ VDD(A). It cannot safely translate 15 V inputs to 5 V outputs; attempting this violates the absolute maximum rating (VDD(A) ≤ VDD(B)) and risks permanent damage.

What is the maximum capacitive load the HEF4104BT,652 can drive while maintaining specified timing?

The datasheet specifies dynamic characteristics up to 50 pF load capacitance (CL) with tr/tf ≤ 20 ns. At VDD = 15 V, tPHL/tPLH remain within 135 ns and output transition times within 40 ns. Driving >50 pF increases propagation delay linearly per the extrapolation formula (e.g., +0.16 ns/pF), potentially violating timing budgets in high-speed designs.

Is VSS the only ground reference, and can it be split between A and B domains?

Yes - VSS (pin 8) is the sole common ground reference for both VDD(A) and VDD(B), all inputs, outputs, and internal circuitry. Splitting or isolating VSS between domains violates the device architecture and will cause malfunction or damage; a single-point, low-impedance ground connection is mandatory.

Does the HEF4104BT,652 require external pull-up or pull-down resistors on its outputs?

No - the HEF4104BT,652 has push-pull complementary outputs (B_n and B̅_n) capable of full rail-to-rail swing without external biasing. Pull-up resistors are unnecessary and may degrade switching speed or increase power consumption; they should only be added if interfacing with open-drain receivers not supported by this device's architecture.