Nexperia USA Inc. HEF4104BT,653

Overview

HEF4104BT,653 from Nexperia is a quad low-to-high voltage translator IC with complementary 3-state outputs (B_n and B̅_n), designed for bidirectional level shifting between two independent supply domains (VDD(A) = 3–15 V, VDD(B) ≥ VDD(A)). It features input clamp diodes enabling safe interfacing to voltages exceeding VDD(A), OE-controlled high-impedance output disable, and operation across -40 °C to +85 °C - used in mixed-voltage microcontroller I/O expansion, legacy bus interfacing, and industrial control backplanes.

For engineers reviewing the HEF4104BT,653 datasheet, HEF4104BT,653 pinout, HEF4104BT,653 application, or HEF4104BT,653 equivalent, key selection criteria include dual-supply voltage translation range (VDD(A)/VDD(B)), complementary 3-state output behavior, input clamping capability, propagation delay vs. load capacitance, and SO16 package thermal and routing constraints.

Technical Context

The HEF4104BT,653 implements four independent CMOS-based level-shifting channels, each accepting TTL/CMOS-compatible inputs at VDD(A) and driving complementary CMOS outputs referenced to VDD(B). Its functional diagram confirms separate A-side (input) and B-side (output) supply rails, with no internal level-shifting circuitry between them - translation relies on native transistor threshold design and external clamping.

Output enable (OE) controls all four channels simultaneously, forcing both B_n and B̅_n into high-impedance states when LOW. Input clamp diodes are integrated on all A_n pins, allowing current-limited connection to signals up to 18 V (per absolute max rating), while static operation ensures zero dynamic power at DC input conditions.

Key Specifications

Pinout & Package

HEF4104BT,653 is housed in a plastic small outline package (SO16), SOT109-1 variant, with 16 leads, 3.9 mm body width, and standard 1.27 mm lead pitch - compatible with automated PCB assembly and IPC-7351B SOIC-16 footprints.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad low-to-high voltage translation applications.

Compared with SN74AVCH4T245RTER and TXS0104EYZTR, the HEF4104BT,653 uniquely supports VDD(B) up to 15 V with complementary outputs and input clamping - making it the only option among the three for translating to industrial 12–15 V logic domains while preserving signal polarity pairs.

Availability

HEF4104BT,653 is available at Aetrix Electronics and suitable for industrial PLC backplanes, legacy microcontroller I/O expansion, automated test equipment signal conditioning, and mixed-voltage sensor hub interfaces requiring stable component supply across extended temperature and voltage ranges.

Supply support for HEF4104BT,653 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable components including logic, discrete, and MOSFET solutions - founded in 2017 as a spin-off from NXP, now serving automotive, industrial, and consumer markets.

The HEF4104BT,653 belongs to Nexperia's HEF4000B logic family, engineered for robust mixed-voltage system integration in industrial control, instrumentation, and legacy interface modernization - emphasizing wide supply tolerance, ESD resilience, and thermal stability.

FAQ

Can HEF4104BT,653 translate from 15 V to 3.3 V?

No - the HEF4104BT,653 is a low-to-high voltage translator only: inputs (A_n) must be referenced to VDD(A), and outputs (B_n/B̅_n) to VDD(B), with VDD(B) ≥ VDD(A). To translate 15 V signals down to 3.3 V, a dedicated high-to-low translator such as the MAX3370 or discrete resistor-divider + buffer is required.

What is the maximum capacitive load the outputs can drive reliably?

The HEF4104BT,653 is characterized up to 50 pF load capacitance (per Table 10), with propagation delays scaling linearly per extrapolation formulas (e.g., tPHL = 69 ns + 0.23 ns/pF × CL at 10 V). Driving >50 pF may exceed 160 ns max delay and increase transition times beyond 60 ns - use series termination or buffer stages for heavier loads.

Is VSS the only ground connection, and must it be common to both supplies?

Yes - VSS (pin 8) is the sole ground reference for the entire device and must be connected to a low-impedance common ground shared by both VDD(A) and VDD(B) supplies. Separating A- and B-side grounds violates the internal substrate biasing and risks latch-up or undefined output states.

Does the OE pin support partial output disabling, or is it all-or-nothing?

OE is global: asserting LOW disables all eight outputs (B₀–B₃ and B̅₀–B̅₃) simultaneously into high-impedance. There is no per-channel enable - if selective channel control is needed, external gating or discrete translators per channel are required.