Nexperia USA Inc. HEF4794BT-Q100J

Overview

HEF4794BT-Q100J from Nexperia is an AEC-Q100 Grade 1 qualified 8-stage serial-in/parallel-out shift-and-store register with open-drain LED driver outputs (QP0–QP7), dual serial outputs (QS1/QS2), and independent strobe (STR) and output enable (OE) controls. It operates from 3 V to 15 V, supports −40 °C to +125 °C ambient, and enables high-speed cascaded LED control in automotive instrument clusters.

For engineers reviewing the HEF4794BT-Q100J datasheet, HEF4794BT-Q100J pinout, HEF4794BT-Q100J application, or HEF4794BT-Q100J equivalent, key selection criteria include its dual-edge serial cascade capability (QS1 on CP↑, QS2 on CP↓), 40 mA per QPn output drive, and automotive-grade ESD robustness (HBM >2000 V, CDM >1000 V).

Technical Context

The device implements a two-stage pipeline: an 8-bit shift register followed by an 8-bit storage latch. Data shifts on rising CP edges and transfers to the latch when STR is HIGH. Outputs are enabled only when OE is HIGH, placing QPn pins in high-impedance state otherwise.

QS1 delivers serial data on each CP↑ for fast-rise-clock systems; QS2 mirrors the same data on the subsequent CP↓, enabling reliable daisy-chaining under slow clock edge conditions. All QPn outputs are open-drain, requiring external pull-ups for LED anode driving or logic-level translation.

Key Specifications

Pinout & Package

HEF4794BT-Q100J is housed in a 16-pin SO16 (SOT109-1) plastic small outline package with 3.9 mm body width, optimized for automated PCB assembly and thermal performance in dense automotive modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 8-bit shift-and-store LED driver applications.

Compared with TLC6C5912QPWRQ1 and STPIC6D595MTR, the HEF4794BT-Q100J uniquely balances automotive qualification, dual-edge cascade capability, and 3–15 V operation-making it optimal for cost-sensitive, mixed-voltage LED control where layout reuse and timing margin are critical.

Availability

HEF4794BT-Q100J is available at Aetrix Electronics and suitable for automotive instrument clusters, industrial panel meters, LED message signs, and automotive exterior lighting requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for HEF4794BT-Q100J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and scalable logic, analog, and MOSFET solutions with deep automotive and industrial heritage.

The HEF4794B-Q100 product line targets automotive-grade serial LED driving applications where functional safety, wide supply tolerance, and robust cascade topology are essential design requirements.

FAQ

What is the minimum pulse width required on the STR input to reliably latch data?

The STR input must remain HIGH for at least 24 ns at VDD = 15 V (per Table 7, tW specification). This ensures full propagation through the internal latch path before the next CP edge. At lower VDD, the required width increases slightly due to slower internal switching; consult Figure 6 and Table 7 for exact values across voltage and temperature.

Can QP0–QP7 outputs drive LEDs directly without external current-limiting resistors?

No. The QPn outputs are open-drain and require external pull-up resistors to set LED current. For example, with VDD = 12 V and a 20 mA target, a 560 Ω resistor yields ~19.3 mA (accounting for VOL ≈ 0.75 V at 20 mA). Direct connection without pull-ups results in no current flow and undefined output states.

How does QS1 differ from QS2 in terms of timing and use case?

QS1 outputs the shifted bit on every CP rising edge, enabling maximum throughput in systems with fast clock edges (>10 ns rise time). QS2 outputs the identical bit on the subsequent CP falling edge, providing deterministic delay for synchronizing cascaded stages when clock rise time exceeds 100 ns - eliminating metastability in slow-edge environments.

Is the HEF4794BT-Q100J compatible with 3.3 V microcontrollers?

Yes. VIH is guaranteed ≥11.0 V at VDD = 15 V but drops to ≥3.5 V at VDD = 5 V and ≥1.5 V at VDD = 3 V (Table 6). A 3.3 V MCU GPIO meets VIH min at VDD ≥ 3 V, and VIL max remains ≤0.4 V across all VDD - ensuring reliable logic-level recognition without level shifters.