Renesas HI1-0303-5
- Part No.:
- HI1-0303-5
- Manufacturer:
- Renesas
- Package:
- 14-CDIP (0.300", 7.62mm)
- Datasheet:
-
HI1-0303-5.pdf
- Description:
- IC SWITCH SPDTX2 50OHM 14CERDIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
HI1-0303-5 from Intersil is a dual SPDT CMOS analog switch fabricated using dielectric isolation technology, designed for precision signal routing in ±15V dual-supply systems. It delivers 35Ω typical on-resistance at 25°C, 40pA leakage at 25°C, and 60ns break-before-make delay - enabling low-distortion switching in sample-and-hold and op amp gain-switching circuits.
For engineers reviewing the HI1-0303-5 datasheet, HI1-0303-5 pinout, HI1-0303-5 application, or HI1-0303-5 equivalent, key selection criteria include its TTL/CMOS-compatible logic interface (0.8V/4V thresholds), symmetrical switch architecture, ±15V analog signal range, and PDIP-14 packaging suitable for industrial temperature operation (0°C to 75°C).
Technical Context
The HI1-0303-5 integrates two independent SPDT analog switches with break-before-make timing control, implemented via matched N- and P-channel MOSFET pairs per switch cell. Each switch exhibits near-constant rON across the full ±15V analog range and supports bidirectional signal flow with identical S/D terminal behavior.
Its digital input buffer includes level-shifting circuitry to interface with TTL logic under ±15V supplies, while charge injection is minimized to 30pC and OFF isolation reaches 60dB at 500kHz - critical for maintaining signal integrity in high-precision analog paths.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Analog Signal Range | ±15V - supports rail-to-rail signal switching without clipping in dual-supply instrumentation. |
| On Resistance (rON) | 35Ω typ @ 25°C - ensures minimal gain error and voltage drop in precision op amp feedback networks. |
| Break-Before-Make Delay | 60ns - prevents momentary shorting between switch paths during state transitions. |
| OFF Leakage Current | 40pA @ 25°C - preserves capacitor charge integrity in sample-and-hold applications over extended hold times. |
| Charge Injection | 30pC - limits voltage glitch on sampled capacitors, reducing settling error in ADC front-ends. |
| Digital Input Thresholds | Logic "0" < 0.8V, Logic "1" > 4V - enables direct interfacing with standard TTL outputs without level-shifting components. |
| Supply Current (I+) | 0.09mA typ @ 25°C - contributes ≤1.0mW total operating power, supporting battery-operated portable designs. |
Pinout & Package
HI1-0303-5 is supplied in a 14-lead plastic dual-in-line package (PDIP) per JEDEC MS-001-AA, with 0.300" wide body and 0.100" lead pitch. The package is RoHS-compliant and Pb-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 14 | IN1, IN2 | Digital control inputs for SW1/SW2 and SW3/SW4 switch pairs; TTL/CMOS compatible. |
| 2, 13 | S1, S2 | Common source terminals of first SPDT switch pair; bidirectional analog signal path. |
| 3, 12 | D1, D2 | Drain terminals (path A) of first SPDT switch pair; connects to selected output when IN = HIGH. |
| 4, 11 | D3, D4 | Drain terminals (path B) of second SPDT switch pair; complementary path to D1/D2. |
| 5, 10 | S3, S4 | Common source terminals of second SPDT switch pair; electrically isolated from S1/S2. |
| 6 | GND | Digital ground reference for logic interface and internal level shifters. |
| 7 | V+ | Positive analog supply (up to +15V); powers switch cells and output drivers. |
| 8 | V− | Negative analog supply (down to −15V); completes dual-supply operation for symmetric signal handling. |
| 9 | NC | No-connect terminal; must remain unconnected to avoid parasitic coupling or latch-up risk. |
Key Features
| Feature | Design Value |
|---|---|
| Symmetrical Switch Elements | Identical on-resistance and capacitance on source and drain terminals - enables flexible bidirectional signal routing without performance penalty. |
| Low Charge Injection (30pC) | Minimizes voltage step on hold capacitors, directly improving accuracy and settling time in sample-and-hold circuits. |
| Break-Before-Make Architecture | Guarantees 60ns minimum dead time between switch openings - eliminates signal shorting in multiplexer or gain-switching configurations. |
| Dielectric Isolation Process | Prevents latch-up and enhances noise immunity in mixed-signal environments with fast digital edges adjacent to sensitive analog nodes. |
| TTL/CMOS Compatibility | Accepts standard 0–5V logic levels without external pull-ups or level translators - simplifies interface design and reduces BOM count. |
Applications
| Sample-and-Hold Circuits | Op Amp Gain Switching |
|---|---|
|
Use Scenario: Capturing and holding analog sensor voltages for successive approximation ADC conversion in data acquisition systems. IC Role / Device Role / Timing Role: Precision analog switch controlling connection between sensor output and hold capacitor; operates in break-before-make mode to prevent charge sharing. Use Value: 40pA leakage at 25°C extends hold time beyond 10 seconds with <1LSB error in 16-bit systems, while 30pC charge injection limits droop-induced offset. |
Use Scenario: Dynamically reconfiguring feedback resistor networks in programmable-gain instrumentation amplifiers for multi-range measurement. IC Role / Device Role / Timing Role: Dual SPDT switch selecting between discrete gain-setting resistors; leverages symmetrical S/D terminals for layout flexibility. Use Value: 35Ω typical rON introduces <0.05% gain error in 10kΩ feedback paths, and ±15V signal range accommodates full-scale outputs up to ±10V. |
| Portable Battery-Powered Instruments | Dual/Single Supply Signal Routing |
|
Use Scenario: Low-power handheld multimeters and portable oscilloscopes requiring long battery life and stable analog switching performance. IC Role / Device Role / Timing Role: Analog multiplexer routing sensor inputs to shared signal conditioning chain; powered from split ±9V alkaline supplies. Use Value: 1.0mW typical operating power minimizes quiescent drain, and 0°C to 75°C rating covers commercial handheld operating envelope without derating. |
Use Scenario: Industrial PLC analog I/O modules supporting both legacy ±15V op amp stages and modern 3.3V/5V microcontroller interfaces. IC Role / Device Role / Timing Role: Level-agnostic signal router isolating ±15V analog paths from digital control logic; uses internal level shifters for TTL compatibility. Use Value: Digital inputs tolerate 0.8V/4V thresholds across full temperature range, and analog ports sustain ±15V signals regardless of logic supply - eliminating external level translation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual SPDT analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADG1434BRUZ | 44V max supply, 3.5Ω rON, 1.8–5.5V logic supply only; requires external VDD/VSS decoupling for ±15V analog rails. | Optimized for low-voltage, high-speed switching (tON = 120ns); not rated for −55°C to 125°C industrial extremes. | Select ADG1434BRUZ when rON < 5Ω and tON < 150ns are mandatory, and system uses separate logic/analog supplies. |
| MAX4634ESE+ | ±15V analog range, 45Ω rON, 30pC charge injection; logic inputs require ≥2.4V for "1", limiting TTL compatibility without pull-ups. | Specified for 0°C to 70°C only; lacks dielectric isolation, increasing latch-up risk in noisy industrial environments. | Choose MAX4634ESE+ for cost-sensitive commercial applications where latch-up immunity is non-critical and TTL drive is supplemented with pull-up resistors. |
Compared with ADG1434BRUZ and MAX4634ESE+, the HI1-0303-5 uniquely combines dielectric isolation, true TTL compatibility (no pull-ups needed), and guaranteed 0°C to 75°C operation in a PDIP package - making it the preferred choice for robust, maintenance-free analog routing in industrial test equipment and legacy instrumentation.
Availability
HI1-0303-5 is available at Aetrix Electronics and suitable for sample-and-hold circuits, op amp gain switching, and portable battery-operated instruments requiring stable component supply across extended production lifecycles.
Supply support for HI1-0303-5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation is a precision analog and power management semiconductor manufacturer, now part of Renesas Electronics, with expertise in high-reliability industrial and aerospace-grade components.
The HI-303 family was engineered for mission-critical analog signal routing in military, avionics, and industrial instrumentation - emphasizing low leakage, rail-to-rail operation, and latch-up immunity under harsh environmental conditions.
FAQ
What is the maximum analog signal voltage supported by the HI1-0303-5?
The HI1-0303-5 supports an analog signal range of ±15V when operated with ±15V supplies. This is specified in the Absolute Maximum Ratings and Electrical Specifications sections of the FN3125 datasheet. Exceeding ±15V on analog terminals risks permanent damage, and the device is not rated for operation beyond this range even with derated supplies.
Does the HI1-0303-5 require external pull-up resistors for TTL logic compatibility?
No, the HI1-0303-5 does not require external pull-up resistors for TTL compatibility. Its digital inputs recognize logic "1" at voltages >4V and logic "0" at <0.8V - matching standard TTL output levels. This is explicitly confirmed in the datasheet's Digital Input Characteristics table and Functional Diagram notes.
What is the thermal resistance (θJA) of the HI1-0303-5 in its PDIP package?
The HI1-0303-5 in the 14-lead PDIP package has a typical junction-to-ambient thermal resistance (θJA) of 90°C/W, as documented in the Thermal Information section of the FN3125 datasheet. This value assumes mounting on a low-thermal-conductivity test board in free air per JEDEC standards.
Can the HI1-0303-5 operate with single-supply configurations?
Yes, the HI1-0303-5 can operate with single-supply configurations, as noted in the Applications section of the datasheet. When using a single +15V supply, V− must be connected to circuit ground, and analog signals must remain within 0V to +15V. Performance parameters like rON and leakage remain valid, but the full ±15V range is unavailable.
Is the HI1-0303-5 RoHS compliant and lead-free?
Yes, the HI1-0303-5 is RoHS compliant and lead-free. The Ordering Information table specifies the HI3-0303-5Z variant as Pb-free, and the datasheet confirms that Intersil Pb-free products use 100% matte tin plating and RoHS-compliant molding compounds - fully satisfying EU Directive 2011/65/EU requirements.
HI1-0303-5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Switch Circuit:
- SPDT
- Multiplexer/Demultiplexer Circuit:
- 2:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 50Ohm
- Channel-to-Channel Matching (ΔRon):
- -
- Voltage - Supply, Single (V+):
- 5V ~ 34V
- Voltage - Supply, Dual (V±):
- ±5V ~ 20V
- Switch Time (Ton, Toff) (Max):
- 300ns, 250ns
- -3db Bandwidth:
- -
- Charge Injection:
- 30pC
- Channel Capacitance (CS(off), CD(off)):
- 16pF, 14pF
- Current - Leakage (IS(off)) (Max):
- 5nA
- Crosstalk:
- -
- Operating Temperature:
- 0°C ~ 75°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 14-CERDIP
HI1-0303-5 FAQ
1.How can I place an order for HI1-0303-5 through Aetrix?
Please submit a Request for Quotation (RFQ) for HI1-0303-5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HI1-0303-5 reliable?
The price and inventory of HI1-0303-5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HI1-0303-5 is usually 5 days.
3.What payment methods are accepted for HI1-0303-5?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HI1-0303-5 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HI1-0303-5?
HI1-0303-5 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HI1-0303-5 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HI1-0303-5?
For technical support, including HI1-0303-5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HI1-0303-5 requirements.
6.How does Aetrix verify that HI1-0303-5 is sourced from the original manufacturer or authorized distributors?
All HI1-0303-5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HI1-0303-5 meets industry standards.
7.What is the process for return or replacement of HI1-0303-5?
All HI1-0303-5 units undergo pre-shipment inspection (PSI). If there is an issue with HI1-0303-5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HI1-0303-5 part is unused and in its original packaging.
Return procedure for HI1-0303-5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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