Renesas HI1-0506-5
- Part No.:
- HI1-0506-5
- Manufacturer:
- Renesas
- Package:
- 28-CDIP (0.600", 15.24mm)
- Datasheet:
-
HI1-0506-5.pdf
- Description:
- IC MUX 16:1 400OHM 28CERDIP
- Quantity:
- Payment:

- Shipping:

Inventory:3,750
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
HI1-0506-5 from Intersil is a single 16-channel CMOS analog multiplexer with ±15V analog signal range, 180Ω typical on-resistance, 250ns access time, and dielectric isolation to prevent latch-up - used in precision data acquisition systems requiring high channel count and rail-to-rail analog switching.
For engineers reviewing the HI1-0506-5 datasheet, HI1-0506-5 pinout, HI1-0506-5 application, or HI1-0506-5 equivalent, this page delivers verified specifications, truth table–aligned digital interface behavior, thermal performance across -55°C to +125°C, and direct replacement guidance for legacy DG506A/DG506AA designs.
Technical Context
The HI1-0506-5 integrates a 4-bit binary decoder, internal +5V logic threshold reference, and 16 analog switches fabricated using Dielectric Isolation (DI) CMOS process - eliminating latch-up and reducing substrate leakage versus junction-isolated alternatives. Its digital inputs include 200Ω series resistors and diode clamps to V+ and V− for transient overvoltage protection.
Switching follows break-before-make timing (80ns tOPEN), supports TTL/CMOS-compatible logic levels (0.8V low / 2.4V high), and maintains <0.03nA off-state input leakage at 25°C - critical for high-impedance sensor front-ends and precision instrumentation signal paths.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Analog Signal Range | ±15V - supports rail-to-rail operation with bipolar supplies, enabling direct interfacing to industrial sensors and DAC outputs without level-shifting. |
| On Resistance (rON) | 180Ω typ - ensures minimal voltage drop and gain error in precision gain-setting or signal routing applications. |
| Access Time (tA) | 250ns max - enables high-speed multiplexing in real-time data acquisition up to ~2 MHz channel update rate. |
| Off Isolation | 68dB at 100kHz - suppresses crosstalk between inactive channels in multi-sensor monitoring systems. |
| Supply Voltage Range | ±10V to ±22V total (V+ to V− ≤ +44V) - accommodates wide-range industrial power rails while maintaining guaranteed logic thresholds. |
| Input Leakage (IA) | 1.0μA max - preserves accuracy in high-impedance measurement nodes such as pH electrodes or piezoelectric transducers. |
| Break-Before-Make Delay | 80ns - prevents momentary short-circuit between channels during address transitions, protecting downstream amplifiers. |
Pinout & Package
HI1-0506-5 is supplied in a 28-lead CERDIP package (PKG DWG # F28.6), rated for -55°C to +125°C operation, with hermetic ceramic sealing and frit-seal lid for long-term reliability in harsh environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 | Analog Inputs IN1–IN16 | 16 independent bidirectional analog switch inputs; each connects to OUT when selected via A0–A3 and EN. |
| 17 | GND | Ground reference for internal logic and substrate bias; must be connected to system ground for proper DI operation. |
| 18 | NC | No connect - internally unconnected; must remain floating per datasheet. |
| 19 | A3 | MSB address bit for 4-bit channel selection (A3–A0); determines which of 16 inputs routes to output. |
| 20 | OUT | Common analog output node; carries selected channel's signal with rON ≤ 300Ω over full temperature range. |
| 21 | IN16 | Redundant labeling of Pin 1 - confirms IN16 mapping aligns with top-view pinout diagram on datasheet Page 3. |
| 22 | +VSUPPLY | Positive supply rail; must be ≥ +10V and ≤ +22V relative to GND for specified operation. |
| 23, 24, 25, 26 | IN15, IN14, IN13, IN12 | Continuation of analog input array; layout matches functional diagram showing contiguous INx routing to decoder. |
| 27 | -VSUPPLY | Negative supply rail; must be ≤ -10V and ≥ -25V relative to GND; substrate tied to this potential per die characteristics. |
| 28 | IN4 | Final listed analog input in top-view sequence; completes 16-input set with correct physical ordering per datasheet Page 3. |
Key Features
| Feature | Design Value |
|---|---|
| Dielectric Isolation (DI) Process | Eliminates latch-up risk and reduces substrate leakage by >10× vs junction-isolated CMOS - essential for mission-critical aerospace and defense systems. |
| Internal +5V Logic Reference | Guarantees TTL/CMOS compatibility without external pull-ups; defines VAL = 0.8V and VAH = 2.4V across full temperature range. |
| Digital Input Protection | 200Ω series resistor + diode clamp to V+/V− limits transient current to safe levels - meets IEC 61000-4-2 Level 3 ESD immunity requirements. |
| Break-Before-Make Switching | 80ns minimum dead time prevents channel overlap - avoids signal corruption in multiplexed ADC sampling or relay-replacement circuits. |
| Low Off-Leakage Performance | 0.03nA typical IS(OFF) at 25°C enables accurate measurement of picoamp-level currents from photodiodes or ion-selective electrodes. |
Applications
| Data Acquisition Systems | Precision Instrumentation |
|---|---|
Use Scenario: Multiplexing 16 thermocouple or RTD inputs into a single high-resolution ADC in an environmental monitoring rack. IC Role / Device Role / Timing Role: Analog signal router with break-before-make timing ensuring no cross-talk between sensor channels during scanning. Use Value: ±15V analog range accepts conditioned sensor outputs directly; 68dB off-isolation prevents thermal EMF coupling between adjacent channels. | Use Scenario: Front-end switching in a portable digital multimeter supporting voltage, current, and resistance measurements. IC Role / Device Role / Timing Role: Precision analog switch matrix selecting test signal path while maintaining nanovolt-level offset stability. Use Value: 0.03nA off-leakage preserves accuracy in high-Z ohmmeter mode; DI process ensures zero latch-up during probe contact bounce. |
| Demultiplexing | Selector Switch |
Use Scenario: Distributing a single DAC output to 16 independent calibration reference points in automated test equipment. IC Role / Device Role / Timing Role: Unidirectional demultiplexer driven by microcontroller GPIOs; EN pin enables synchronized channel activation. Use Value: 250ns access time allows sub-microsecond channel switching; 180Ω rON minimizes gain error in precision reference distribution. | Use Scenario: Manual or software-controlled signal source selection in a lab-grade function generator with multiple waveform inputs. IC Role / Device Role / Timing Role: High-fidelity analog selector with rail-to-rail signal handling and low THD due to matched P/N switch geometry. Use Value: ±15V range accommodates both sine and square wave amplitudes up to 30Vpp; DI process ensures stable performance under repeated hot-plug events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HI1-0506-2 | Same die, CERDIP package, extended -55°C to +125°C temp range; no Pb-free marking. | Preferred for military/aerospace deployments requiring full military temperature compliance and hermetic reliability. | Select HI1-0506-2 if operating beyond 0°C to +75°C or requiring non-RoHS-compliant legacy qualification. |
| DG506A | Pin-compatible but junction-isolated; higher substrate leakage, no internal 5V reference - requires external pull-ups. | Suitable only for commercial-temp, non-latch-up-sensitive applications where DI is not mandated. | Choose DG506A only for cost-sensitive, non-critical industrial designs where latch-up risk is mitigated externally. |
Compared with HI1-0506-2, HI1-0506-5 offers RoHS-compliant Pb-free finish and validated 0°C to +75°C operation, while DG506A lacks dielectric isolation and internal logic reference - making HI1-0506-5 the sole choice for high-reliability, latch-up-immune, and simplified interface designs.
Availability
HI1-0506-5 is available at Aetrix Electronics and suitable for data acquisition systems, precision instrumentation, demultiplexing architectures, and selector switch implementations requiring stable component supply across extended lifecycle programs.
Supply support for HI1-0506-5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation is a leading provider of precision analog and power management solutions, acquired by Renesas Electronics in 2017 and integrated into its analog product portfolio.
The HI-506 family was designed specifically for high-channel-count, high-reliability analog signal routing in industrial, aerospace, and test equipment - emphasizing latch-up immunity, wide supply tolerance, and low leakage.
FAQ
What is the maximum supply voltage rating for HI1-0506-5?
The HI1-0506-5 supports a maximum V+ to V− differential of +44V, with individual rail limits of +22V (V+ to GND) and -25V (V− to GND). Operation outside these absolute maximum ratings risks permanent damage. The device is typically operated at ±15V or ±12V for optimal rON and leakage performance, as confirmed in the Electrical Specifications table on datasheet page 8.
Does HI1-0506-5 require external pull-up resistors on its address lines?
No, HI1-0506-5 does not require external pull-up resistors on A0–A3 or EN because it includes an internal +5V reference that sets guaranteed logic thresholds (VAL = 0.8V, VAH = 2.4V). This feature enables direct interface with TTL, CMOS, DTL, and some PMOS logic families - explicitly stated in the Functional Description section on datasheet page 1.
What is the meaning of "Dielectric Isolation" in HI1-0506-5, and why does it matter?
Dielectric Isolation (DI) in HI1-0506-5 replaces conventional junction isolation with silicon dioxide trenches, eliminating parasitic thyristor paths that cause latch-up. As noted on datasheet page 1, DI also reduces substrate leakage and parasitic capacitance - critical for high-precision, high-voltage, or radiation-prone applications where failure modes must be physically prevented, not just mitigated.
Can HI1-0506-5 handle analog signals exceeding the supply rails?
No, HI1-0506-5 analog inputs and outputs must remain within (V− −2V) to (V+ +2V) per Absolute Maximum Ratings on datasheet page 8. Signals exceeding these limits forward-bias internal clamping diodes and may exceed the 20mA continuous current rating. For overvoltage-tolerant operation, Intersil recommends the HI-546 series - explicitly cited on datasheet page 1 as the designated alternative.
How does the break-before-make timing of HI1-0506-5 affect system design?
The HI1-0506-5 guarantees a minimum 80ns break-before-make delay (tOPEN) between channel disconnect and reconnect, preventing momentary shorts during address changes. This eliminates the need for external blanking logic in time-critical applications like multiplexed ADC sampling or relay emulation - a key timing parameter verified in the Dynamic Characteristics table on datasheet page 8.
HI1-0506-5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Switch Circuit:
- -
- Multiplexer/Demultiplexer Circuit:
- 16:1
- Number of Circuits:
- 1
- On-State Resistance (Max):
- 400Ohm
- Channel-to-Channel Matching (ΔRon):
- 20Ohm
- Voltage - Supply, Single (V+):
- -
- Voltage - Supply, Dual (V±):
- ±15V
- Switch Time (Ton, Toff) (Max):
- 250ns, 250ns (Typ)
- -3db Bandwidth:
- -
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- 10pF, 52pF
- Current - Leakage (IS(off)) (Max):
- 30pA (Typ)
- Crosstalk:
- -
- Operating Temperature:
- 0°C ~ 75°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-CerDip
HI1-0506-5 FAQ
1.How can I place an order for HI1-0506-5 through Aetrix?
Please submit a Request for Quotation (RFQ) for HI1-0506-5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HI1-0506-5 reliable?
The price and inventory of HI1-0506-5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HI1-0506-5 is usually 5 days.
3.What payment methods are accepted for HI1-0506-5?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HI1-0506-5 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HI1-0506-5?
HI1-0506-5 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HI1-0506-5 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HI1-0506-5?
For technical support, including HI1-0506-5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HI1-0506-5 requirements.
6.How does Aetrix verify that HI1-0506-5 is sourced from the original manufacturer or authorized distributors?
All HI1-0506-5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HI1-0506-5 meets industry standards.
7.What is the process for return or replacement of HI1-0506-5?
All HI1-0506-5 units undergo pre-shipment inspection (PSI). If there is an issue with HI1-0506-5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HI1-0506-5 part is unused and in its original packaging.
Return procedure for HI1-0506-5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
HI1-0506-5 Tags

-
SN74LVC1G3157DBVR
Texas Instruments
-
SN74LVC1G66DBVR
Texas Instruments
-
SN74LVC1G66DCKR
Texas Instruments

-
SN74LVC1G3157DSFR
Texas Instruments

-
1P1G3157QDCKRQ1
Texas Instruments

-
SN74LVC2G66DCUR
Texas Instruments
-
SN74LV4052APWR
Texas Instruments

-
74HC4051D,653
Nexperia USA Inc.
-
SN74LV4051APWR
Texas Instruments
-
CD74HC4052PWR
Texas Instruments
-
CD74HC4051PWR
Texas Instruments
-
TS5A3166DBVR
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

