Renesas HI1-0509A-5
- Part No.:
- HI1-0509A-5
- Manufacturer:
- Renesas
- Package:
- 16-CDIP (0.300", 7.62mm)
- Datasheet:
-
HI1-0509A-5.pdf
- Description:
- IC SW SP4TX2 1.8KOHM 16CERDIP
- Quantity:
- Payment:

- Shipping:

Inventory:3,289
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Product details
Overview
HI1-0509A-5 from Intersil is a differential 4-channel CMOS analog multiplexer with active overvoltage protection, designed for fault-tolerant signal routing in mixed-supply systems. It supports ±15V analog signal range, withstands continuous ±33V overvoltage on inputs, features 12pF channel output capacitance, 1.5kΩ typical on-resistance at +25°C, and operates across 0°C to +75°C. It is used in industrial telemetry interfaces where external sensors may exceed supply rails.
For engineers reviewing the HI1-0509A-5 datasheet, HI1-0509A-5 pinout, HI1-0509A-5 application, or HI1-0509A-5 equivalent, key selection criteria include differential channel count, ±33V overvoltage tolerance, break-before-make switching, CERDIP package thermal performance, and compatibility with ±15V dual supplies in safety-critical data acquisition paths.
Technical Context
The HI1-0509A-5 implements dielectrically isolated CMOS (CMOS-DI) technology with integrated overvoltage clamping and signal isolation circuitry. Its functional diagram shows dedicated level shifters for TTL-compatible address inputs, a 2-bit decoder driving differential switch pairs, and independent protection networks per channel that maintain 1kΩ input resistance during supply loss.
It uses break-before-make switching with 80ns typical tOPEN, supports 500ns access time at 4V logic high, and maintains <100nA off-output leakage under full temperature range. The VREF pin is uncommitted and left open per default operation, and digital inputs tolerate faults up to 4V beyond either supply rail.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Analog Channels | Differential 4-channel (two matched pairs: IN1A/IN1B through IN4A/IN4B) |
| Analog Signal Range | ±15V - supports full-rail operation with ±15V dual supplies |
| Overvoltage Protection | ±33V continuous - prevents damage and channel interaction when inputs exceed supplies |
| On Resistance | 1.5 kΩ typ @ +25°C - ensures minimal gain error and voltage drop in precision signal paths |
| Access Time | 500 ns max - enables sampling rates up to ~2 MSPS in time-critical multiplexed systems |
| Off Output Leakage | 100 nA max @ full temp range - preserves accuracy in high-impedance sensor front-ends |
| Package | 16-lead CERDIP (F16.3) - hermetic, high-reliability ceramic package rated for 0°C to +75°C |
Pinout & Package
HI1-0509A-5 is housed in a 16-lead Ceramic Dual-In-Line Package (CERDIP), F16.3 drawing, with 0.300" body width, 0.125"–0.200" lead length, and notch-indexed pin 1. Thermal resistance θJA = 75°C/W, θJC = 22°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | +VSUPPLY | Positive analog supply connection; must be ≤ +22V relative to GND |
| 2 | OUT A | Differential output terminal A - routed from selected INxA pair |
| 3 | IN 1B | Negative input of Channel 1 differential pair |
| 4 | IN 2B | Negative input of Channel 2 differential pair |
| 5 | IN 3B | Negative input of Channel 3 differential pair |
| 6 | IN 4B | Negative input of Channel 4 differential pair |
| 7 | A0 | LSB address input - selects channel pair (00=Ch1, 01=Ch2, 10=Ch3, 11=Ch4) |
| 8 | A1 | MSB address input - used with A0 for 2-bit binary decoding |
| 9 | ENABLE | Active-high enable - disables all switches when low; no latch-up on power loss |
| 10 | GND | Analog ground reference - common return for supplies and signal paths |
| 11 | IN 4A | Positive input of Channel 4 differential pair |
| 12 | IN 3A | Positive input of Channel 3 differential pair |
| 13 | IN 2A | Positive input of Channel 2 differential pair |
| 14 | IN 1A | Positive input of Channel 1 differential pair |
| 15 | -VSUPPLY | Negative analog supply connection; must be ≥ -25V relative to GND |
| 16 | OUT B | Differential output terminal B - complementary to OUT A |
Key Features
| Feature | Design Value |
|---|---|
| Active Overvoltage Protection | ±33V continuous input tolerance without degradation - eliminates need for external clamps in field-connected sensor systems |
| No Channel Interaction During Fault | Isolated protection per channel - prevents fault propagation between differential pairs during overvoltage events |
| Fail-Safe with Power Loss | 1kΩ input resistance maintained on all channels when supplies are absent - avoids floating inputs and system instability |
| Break-Before-Make Switching | 80ns minimum tOPEN - prevents momentary shorting between differential channel outputs during address changes |
| Dielectrically Isolated CMOS | 44V maximum V+ to V− rating - enables robust operation in high-voltage industrial environments |
Applications
| Industrial Data Acquisition | Remote Sensor Telemetry |
|---|---|
|
Use Scenario: Multiplexing differential outputs from four isolated RTD or strain gauge bridges into a single ADC front-end. IC Role / Device Role / Timing Role: Differential analog switch enabling sequential sampling of high-precision sensor pairs while rejecting common-mode noise. Use Value: ±33V overvoltage tolerance protects against induced transients on long sensor cables; 12pF CD(OFF) minimizes crosstalk between active and inactive channels. |
Use Scenario: Routing differential signals from geographically dispersed environmental sensors (temperature, pressure, humidity) to a central monitoring unit. IC Role / Device Role / Timing Role: Fault-tolerant signal router handling externally powered sensor nodes that may operate outside system supply rails. Use Value: Fail-safe 1kΩ input impedance prevents signal corruption during brownout; break-before-make timing avoids inter-channel coupling during address transitions. |
| Avionics Signal Conditioning | Test Equipment Multiplexing |
|
Use Scenario: Selecting among four differential engine-monitoring transducers (vibration, oil pressure, exhaust gas temp) in a flight data recorder interface. IC Role / Device Role / Timing Role: High-reliability analog switch ensuring signal integrity under EMI-rich avionics bus environments. Use Value: Hermetic CERDIP package provides moisture resistance and thermal stability; ±15V signal range matches legacy aircraft sensor standards. |
Use Scenario: Automated test system switching between four differential calibration sources during self-test sequences. IC Role / Device Role / Timing Role: Precision multiplexer enabling traceable, low-leakage path selection for metrology-grade measurements. Use Value: <100nA off-output leakage preserves source accuracy; 500ns access time supports rapid test sequencing without settling delays. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar differential analog multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HI3-0509A-5 | Same die, but in 16-lead PDIP (E16.3) instead of CERDIP; higher θJA = 90°C/W; not rated for extended temperature or hermetic use | Suitable for cost-sensitive commercial bench equipment; lacks CERDIP's moisture resistance and thermal stability | Select HI3-0509A-5 only if RoHS-compliant through-hole assembly and lower cost outweigh reliability requirements. |
| ADG509F | 4-channel differential mux with ±15V signal range, but only ±20V overvoltage rating; 25pF CD(OFF); no fail-safe 1kΩ input on supply loss | Used in general-purpose lab instruments where transient immunity is less critical than channel count density | Choose ADG509F only if board space constraints favor SOIC-16 and ±20V overvoltage margin is sufficient for the application. |
Compared with HI3-0509A-5 and ADG509F, the HI1-0509A-5 uniquely combines hermetic CERDIP packaging, ±33V overvoltage tolerance, and fail-safe 1kΩ input impedance - making it the sole option for high-reliability, field-deployed differential multiplexing where supply loss or cable-induced transients are probable.
Availability
HI1-0509A-5 is available at Aetrix Electronics and suitable for industrial data acquisition, remote sensor telemetry, and avionics signal conditioning requiring stable component supply across extended product lifecycles.
Supply support for HI1-0509A-5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation is a U.S.-based semiconductor manufacturer specializing in high-performance analog and mixed-signal ICs, now part of Renesas Electronics.
The HI-509A family was designed specifically for fault-tolerant analog signal routing in harsh environments - emphasizing overvoltage resilience, channel isolation, and operation across wide temperature ranges in industrial and aerospace systems.
FAQ
What is the maximum continuous overvoltage the HI1-0509A-5 can withstand on its analog inputs?
The HI1-0509A-5 can withstand continuous ±33V on its analog inputs relative to its supplies, as confirmed in the Absolute Maximum Ratings table and Figure 3A of FN3143 Rev.6.00. This applies to both INxA and INxB pins simultaneously and is independent of whether the device is enabled or disabled. Operation beyond this limit risks permanent damage.
Does the HI1-0509A-5 require an external VREF connection for normal operation?
No, the HI1-0509A-5 does not require an external VREF connection for standard operation. Per the Electrical Specifications section, VREF is specified as "Open" in all test conditions, and the functional diagram shows no internal dependency on VREF for switching or protection functions. Leaving VREF unconnected is the default configuration.
What is the purpose of the 1kΩ resistance specified during supply loss for the HI1-0509A-5?
The 1kΩ resistance is the fail-safe input impedance presented by each analog terminal (INxA, INxB, OUTA, OUTB) when either +VSUPPLY or -VSUPPLY is absent. As stated in the datasheet, this prevents floating inputs and protects connected signal sources from short-circuiting - a critical feature for systems where sensor modules remain powered while the multiplexer supply is interrupted.
Can the HI1-0509A-5 be used with single-supply operation, such as 0V and +30V?
No. The HI1-0509A-5 requires dual symmetric supplies (e.g., ±15V) per its Absolute Maximum Ratings: V+ to GND ≤ +22V and V− to GND ≥ −25V. A 0V/+30V configuration violates the −25V limit on V− to GND and exceeds the +22V limit on V+ to GND. It must be operated with true bipolar rails centered near ground.
How does the break-before-make timing of the HI1-0509A-5 prevent signal corruption?
The HI1-0509A-5 guarantees a minimum 80ns break interval (tOPEN) between disconnecting one differential channel pair and connecting the next. This prevents momentary shorts between OUTA/OUTB nodes of different channels during address transitions - preserving signal integrity in applications like differential ADC sampling where channel crosstalk would introduce measurement errors.
HI1-0509A-5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Switch Circuit:
- SP4T
- Multiplexer/Demultiplexer Circuit:
- 4:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 1.8kOhm
- Channel-to-Channel Matching (ΔRon):
- -
- Voltage - Supply, Single (V+):
- -
- Voltage - Supply, Dual (V±):
- ±15V
- Switch Time (Ton, Toff) (Max):
- 300ns, 300ns (Typ)
- -3db Bandwidth:
- -
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- 10pF, 12pF
- Current - Leakage (IS(off)) (Max):
- 30pA (Typ)
- Crosstalk:
- -
- Operating Temperature:
- 0°C ~ 75°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-CERDIP
HI1-0509A-5 FAQ
1.How can I place an order for HI1-0509A-5 through Aetrix?
Please submit a Request for Quotation (RFQ) for HI1-0509A-5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HI1-0509A-5 reliable?
The price and inventory of HI1-0509A-5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HI1-0509A-5 is usually 5 days.
3.What payment methods are accepted for HI1-0509A-5?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HI1-0509A-5 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HI1-0509A-5?
HI1-0509A-5 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HI1-0509A-5 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HI1-0509A-5?
For technical support, including HI1-0509A-5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HI1-0509A-5 requirements.
6.How does Aetrix verify that HI1-0509A-5 is sourced from the original manufacturer or authorized distributors?
All HI1-0509A-5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HI1-0509A-5 meets industry standards.
7.What is the process for return or replacement of HI1-0509A-5?
All HI1-0509A-5 units undergo pre-shipment inspection (PSI). If there is an issue with HI1-0509A-5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HI1-0509A-5 part is unused and in its original packaging.
Return procedure for HI1-0509A-5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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