Renesas HI3-0516-5
- Part No.:
- HI3-0516-5
- Manufacturer:
- Renesas
- Package:
- 28-DIP (0.600", 15.24mm)
- Datasheet:
-
HI3-0516-5.pdf
- Description:
- IC MUX 16:1 750OHM 28DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
HI3-0516-5 from Intersil is a monolithic, dielectrically isolated CMOS analog multiplexer configured as either a 16-channel single-ended or 8-channel differential switch. It features built-in address decoding, an inhibit input, selectable logic level (TTL/CMOS), and dual-mode operation via A3 pin configuration. Key confirmed specs include 130ns typical access time, 250ns settling to 0.1%, and <100pA off-state output leakage at 25°C - enabling use in high-speed data acquisition systems.
For engineers reviewing the HI3-0516-5 datasheet, HI3-0516-5 pinout, HI3-0516-5 application, or HI3-0516-5 equivalent, this device supports critical timing-sensitive analog signal routing where low charge injection (≤20mV), high off-isolation (≥55dB at 500kHz), and sub-nanosecond settling are required for precision instrumentation and industrial control interfaces.
Technical Context
The HI3-0516-5 implements dual independent 8-channel multiplexers (MUX A/B) with shared address inputs A0–A2 and mode-selectable A3/SDS pin. Its dielectric isolation process minimizes substrate leakage and parasitic capacitance, delivering stable performance across ±15V analog signal ranges and full 0°C to 75°C operating temperature.
Logic-level selection is hardware-configured via VDD/LLS pin: grounded for TTL-compatible thresholds (VAL = 0.8V, VAH = 2.4V), tied to VDD for CMOS thresholds (VAL = 0.3VDD, VAH = 0.7VDD). Channel enable is controlled by an active-high EN input, with break-before-make delay ≤20ns ensuring no signal shorting during switching.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Access Time | 130ns typical - enables sampling rates up to ~7.7MHz in burst-mode acquisition |
| Settling Time (0.1%) | 250ns - ensures accurate digitization of fast-changing analog signals without post-switching error |
| Off Isolation | 55dB minimum at 500kHz - suppresses crosstalk between unselected channels in multi-signal systems |
| Charge Injection Error | 20mV maximum - limits baseline shift in sample-and-hold or switched-capacitor circuits |
| On Resistance | 620Ω typical - maintains signal integrity for low-current sensor interfaces and precision voltage routing |
| Off Leakage Current | ID(OFF) < 100pA at 25°C - preserves accuracy in high-impedance measurement paths (e.g., pH sensors) |
| Analog Signal Range | ±15V - supports rail-to-rail operation with standard bipolar supplies in industrial signal chains |
Pinout & Package
HI3-0516-5 is housed in a 28-lead plastic dual in-line package (PDIP), per package drawing E28.6. Pin functions are validated per FN3146 Rev 4.00 datasheet and functional block diagram.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V+ | Positive Analog Supply | Accepts +15V supply; powers internal analog switches and bias circuitry |
| V- | Negative Analog Supply | Accepts -15V supply; defines lower rail for bipolar analog signal handling |
| OUT A / OUT B | Differential Output Terminals | Provide complementary outputs when used in differential mode; tied together for single-ended operation |
| A0–A2 | Binary Address Inputs | Select one of eight channels per MUX bank; decoded internally without external logic |
| A3/SDS | Mode Select / Single-Ended-Differential Switch | Grounded or connected to V− for differential 8-channel mode; used as address bit for 16-channel mode |
| ENABLE | Channel Enable Control | Active-high signal disables all switches when low - essential for power gating and system synchronization |
| VDD/LLS | Logic Level Selection | GND = TTL compatibility; VDD = CMOS compatibility - sets input threshold voltages dynamically |
| GND | Digital Ground Reference | Provides return path for digital control signals; isolated from analog ground in layout best practice |
| IN 1A–IN 8A / IN 1B–IN 8B | Analog Input Channels | 16 total inputs mapped as eight differential pairs (e.g., IN 1A/IN 1B = Channel 1 differential pair) |
Key Features
| Feature | Design Value |
|---|---|
| Dielectric Isolation Process | Reduces substrate leakage and parasitic capacitance - improves channel-to-channel isolation and DC accuracy |
| Programmable Single-Ended/Differential Mode | A3 pin configures device as either 16:1 single-ended or 8:1 differential mux - eliminates need for two separate parts |
| TTL/CMOS Logic-Level Selectability | VDD/LLS pin selects input thresholds - simplifies interface to mixed-voltage controller systems without level shifters |
| Low Charge Injection (≤20mV) | Minimizes transient errors in sample-and-hold stages - critical for high-resolution ADC front-ends |
| Break-Before-Make Switching | tOPEN ≤20ns - prevents momentary shorting between channels during address changes, protecting downstream circuitry |
Applications
| Data Acquisition Systems | Precision Instrumentation |
|---|---|
Use Scenario: High-speed scanning of multiple sensor outputs (e.g., thermocouples, strain gauges) into a single ADC channel. IC Role / Device Role / Timing Role: Analog signal router that sequentially connects 16 sensor nodes to a shared precision ADC while maintaining signal fidelity. Use Value: 250ns settling to 0.1% and <100pA off-leakage ensure minimal measurement error and channel crosstalk in 16-channel scan cycles. | Use Scenario: Front-end multiplexing in benchtop multimeters or calibration equipment requiring differential input rejection. IC Role / Device Role / Timing Role: Dual 8-channel differential switch enabling true differential measurements with common-mode noise cancellation. Use Value: 55dB off-isolation at 500kHz and matched on-resistance (620Ω typ.) preserve CMRR and gain accuracy across all channels. |
| Industrial Process Control | Automated Test Equipment (ATE) |
Use Scenario: Routing analog feedback signals from PLC I/O modules to centralized monitoring and control units. IC Role / Device Role / Timing Role: Robust analog switch interfacing field transmitters (4–20mA loops, RTDs) with isolated microcontroller ADCs. Use Value: ±15V analog range and dielectric isolation support direct connection to industrial-grade sensors without signal conditioning. | Use Scenario: Signal path selection in automated test fixtures verifying mixed-signal ICs under varying voltage and timing conditions. IC Role / Device Role / Timing Role: Precision analog switch enabling rapid reconfiguration of stimulus/response paths during parametric testing. Use Value: 130ns access time and 20ns break-before-make delay allow sub-microsecond channel switching synchronized to test clock edges. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DG406 | Single-ended 16-channel only; no differential mode; higher on-resistance (100Ω min vs. 620Ω typ.); no SDS or LLS features | Lacks A3/SDS and VDD/LLS flexibility - requires external logic for mode selection and level translation | Choose DG406 only if single-ended operation suffices and lower on-resistance is prioritized over isolation and leakage specs |
| DG407 | Dual 8-channel differential only; fixed differential topology; no A3 programmability; same on-resistance profile as DG406 | No single-ended option; incompatible pinout and control scheme - not drop-in replaceable | Select DG407 when differential-only routing is mandatory and board layout allows redesign for dedicated differential channel mapping |
Compared with DG406 and DG407, the HI3-0516-5 uniquely combines single-ended/differential configurability, logic-level adaptability, and dielectric isolation - making it suitable for designs requiring both flexibility and high-precision analog switching without compromising leakage or settling performance.
Availability
HI3-0516-5 is available at Aetrix Electronics and suitable for data acquisition systems, precision instrumentation, and industrial process control requiring stable component supply and long-term obsolescence management.
Supply support for HI3-0516-5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation is a U.S.-based semiconductor company specializing in high-performance analog and mixed-signal ICs, acquired by Renesas Electronics in 2017.
The HI-516 product line was designed for high-speed, low-leakage analog signal routing in precision measurement and industrial control systems - emphasizing dielectric isolation, configurable topology, and robust bipolar supply operation.
FAQ
What is the operating temperature range for HI3-0516-5?
The HI3-0516-5 is rated for operation from 0°C to +75°C, as specified in the FN3146 Rev 4.00 datasheet. This commercial temperature grade makes it suitable for indoor industrial and laboratory environments but not extended-temperature applications such as automotive under-hood or military deployments. The device's thermal resistance (θJA = 60°C/W) assumes mounting on an evaluation PCB in free air.
How does the A3/SDS pin configure HI3-0516-5 for single-ended versus differential operation?
When A3/SDS is used as a digital address input (e.g., tied to logic high/low), the HI3-0516-5 operates as a 16-channel single-ended multiplexer with OUT A and OUT B tied together. When A3/SDS is connected to V−, it enables 8-channel differential mode - selecting matched input pairs (e.g., IN 1A/IN 1B) simultaneously. This dual-mode capability is intrinsic to the HI3-0516-5's internal decoder architecture.
Does HI3-0516-5 support both TTL and CMOS logic levels, and how is this selected?
Yes, HI3-0516-5 supports both TTL and CMOS logic levels via the VDD/LLS pin. Grounding or leaving VDD/LLS open configures TTL thresholds (VAL = 0.8V, VAH = 2.4V); connecting it to VDD selects CMOS thresholds (VAL = 0.3VDD, VAH = 0.7VDD). This hardware-selectable feature eliminates external level-shifting components when interfacing with diverse microcontrollers or FPGAs.
What is the maximum analog signal voltage range supported by HI3-0516-5?
The HI3-0516-5 supports an analog signal range of ±15V, defined as (V−) −2V to (V+) +2V per absolute maximum ratings. With standard ±15V supplies applied to V+ and V−, the device reliably passes signals from −15V to +15V - making it compatible with legacy industrial sensor interfaces, op-amp outputs, and bipolar DACs without attenuation or clamping.
Is HI3-0516-5 pin-compatible with DG406 or DG407 as a drop-in replacement?
No, HI3-0516-5 is not pin-compatible with DG406 or DG407. While all three are 28-pin PDIP analog multiplexers, HI3-0516-5 has unique pin assignments - including dedicated VDD/LLS, A3/SDS, and dual output terminals (OUT A/OUT B) - that differ from DG406/DG407 pinouts. Board-level redesign is required to substitute HI3-0516-5 for either alternative.
HI3-0516-5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Switch Circuit:
- -
- Multiplexer/Demultiplexer Circuit:
- 16:1
- Number of Circuits:
- 1
- On-State Resistance (Max):
- 750Ohm
- Channel-to-Channel Matching (ΔRon):
- -
- Voltage - Supply, Single (V+):
- -
- Voltage - Supply, Dual (V±):
- ±15V
- Switch Time (Ton, Toff) (Max):
- 175ns, 175ns
- -3db Bandwidth:
- -
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- 10pF, 25pF (Max)
- Current - Leakage (IS(off)) (Max):
- 10pA (Typ)
- Crosstalk:
- -
- Operating Temperature:
- 0°C ~ 75°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-PDIP
HI3-0516-5 FAQ
1.How can I place an order for HI3-0516-5 through Aetrix?
Please submit a Request for Quotation (RFQ) for HI3-0516-5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HI3-0516-5 reliable?
The price and inventory of HI3-0516-5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HI3-0516-5 is usually 5 days.
3.What payment methods are accepted for HI3-0516-5?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HI3-0516-5 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HI3-0516-5?
HI3-0516-5 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HI3-0516-5 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HI3-0516-5?
For technical support, including HI3-0516-5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HI3-0516-5 requirements.
6.How does Aetrix verify that HI3-0516-5 is sourced from the original manufacturer or authorized distributors?
All HI3-0516-5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HI3-0516-5 meets industry standards.
7.What is the process for return or replacement of HI3-0516-5?
All HI3-0516-5 units undergo pre-shipment inspection (PSI). If there is an issue with HI3-0516-5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HI3-0516-5 part is unused and in its original packaging.
Return procedure for HI3-0516-5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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