Renesas HI5767EVAL2

Overview

HI5767EVAL2 from Intersil is an evaluation board designed to demonstrate the HI5767 - a monolithic 10-bit, 60MSPS pipelined analog-to-digital converter with internal 2.5V band-gap reference, 250MHz full-power input bandwidth, and differential or single-ended analog input capability. It supports TTL/CMOS-compatible digital outputs at 3.0V or 5.0V and delivers 8.4-bit ENOB at 60MSPS/10MHz input for high-speed communications and video digitizing applications.

For engineers reviewing the HI5767EVAL2 datasheet, HI5767EVAL2 pinout, HI5767EVAL2 application, or HI5767EVAL2 equivalent, this board enables rapid validation of the HI5767 ADC's dynamic performance (SINAD = 53.8dB, SFDR = 67dBc), latency (7 clock cycles), and interface timing under real-world signal conditions including QAM demodulation and IF sampling.

Technical Context

The HI5767EVAL2 implements a complete signal chain around the HI5767 ADC, featuring BNC analog inputs, on-board clock conditioning, decoupling capacitors (10µF + 0.1µF per supply rail), and configurable OE/DFS control headers. It routes all 28 pins of the SOIC-packaged HI5767, including dual digital supplies (DVCC1/DVCC2), separate analog/digital grounds (AGND/DGND), and VREFIN/VREFOUT loopback for internal reference operation.

Designed for 60MSPS operation, the board supports both offset binary and two's complement output formats via the DFS jumper, and provides OE-controlled three-state digital outputs compatible with 3.0V or 5.0V logic families. The layout follows high-speed ADC best practices: analog and digital sections are partitioned, ground planes are split but joined at a single point, and critical analog traces (VIN+, VIN−, VDC) are length-matched and shielded from digital noise sources.

Key Specifications

Availability

HI5767EVAL2 is available at Aetrix Electronics and suitable for high-speed data acquisition, professional video digitizing, and digital communication system development requiring stable component supply and validated reference designs for pipeline ADCs.

Supply support for HI5767EVAL2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Intersil Corporation (now part of Renesas Electronics) is a U.S.-based semiconductor company specializing in precision analog, power management, and high-speed data conversion ICs for industrial, communications, and test equipment markets.

The HI5767EVAL2 belongs to Intersil's high-speed ADC evaluation platform family, engineered specifically to accelerate prototyping and characterization of pipeline ADCs in demanding RF, IF, and video signal chains where dynamic performance and low-latency sampling are critical.

FAQ

What is the primary function of the HI5767EVAL2 evaluation board?

The HI5767EVAL2 evaluation board is a fully assembled and tested platform for evaluating the HI5767 10-bit, 60MSPS pipelined analog-to-digital converter. It provides BNC analog inputs, configurable digital output voltage (3.0V/5.0V), on-board clock conditioning, and proper grounding/supply decoupling to validate dynamic performance metrics such as ENOB (8.4 bits), SINAD (53.8 dB), and SFDR (67 dBc) under real-world signal conditions. The board directly supports the HI5767 device in its 28-lead SOIC package.

Does the HI5767EVAL2 support both differential and single-ended analog input configurations?

Yes, the HI5767EVAL2 supports both configurations. For differential input, it uses the VIN+ and VIN− BNC connectors with internal VDC (3.0V) biasing, enabling ±0.5V full-scale differential range. For single-ended input, the board allows connection to VIN+ while referencing VIN− to VDC, supporting up to 1.0Vpp input. The schematic and layout follow Intersil's recommended practices for each mode, including matching, decoupling, and common-mode voltage compliance (0.25V to 4.75V).

How is the internal 2.5V reference configured on the HI5767EVAL2?

The HI5767EVAL2 configures the HI5767's internal 2.5V band-gap reference by default via direct loopback: VREFOUT (Pin 8) is hardwired to VREFIN (Pin 7). This eliminates need for external reference components and ensures stable 2.5V reference operation across temperature (±120 ppm/°C typical drift). An optional header allows replacement with an external 2.5V reference if higher precision or lower noise is required, with appropriate 0.1µF bypass capacitor installed at VREFOUT.

What digital interface options does the HI5767EVAL2 provide for connecting to FPGA or ASIC logic?

The HI5767EVAL2 provides 10-bit parallel CMOS/TTL-compatible digital outputs (D0–D9), with OE (output enable) and DFS (data format select) control headers. DVCC2 can be set to either +3.0V or +5.0V to match target logic levels. Outputs are latched with 7-cycle latency synchronized to the sample clock (CLK), and support both offset binary (DFS = LOW) and two's complement (DFS = HIGH) formats. All signals are routed to 0.1" headers with impedance-controlled traces for reliable interfacing.

Is the HI5767EVAL2 compatible with other members of the HI5767 family beyond the 60MSPS variant?

Yes - the HI5767EVAL2 is mechanically and electrically compatible with all HI5767 variants (20/40/60MSPS), as they share identical 28-lead SOIC packaging, pinout, supply requirements (AVCC = DVCC1 = +5V), and functional interface. While optimized for 60MSPS operation per ordering code HI5767/6CB, the board supports lower sampling rates without modification. Performance metrics (e.g., ENOB, SINAD) will scale per the specific variant's datasheet specifications.