Renesas HI9P0509-5
- Part No.:
- HI9P0509-5
- Manufacturer:
- Renesas
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
HI9P0509-5.pdf
- Description:
- IC SWITCH SP4T X 2 400OHM 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,357
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
HI9P0509-5 from Intersil is a 4-channel differential CMOS analog multiplexer with ±15V analog signal range, 180Ω typical on-resistance, 250ns access time, and break-before-make switching. It operates across -40°C to +85°C and is used in precision instrumentation for channel-selecting differential sensor signals.
For engineers reviewing the HI9P0509-5 datasheet, HI9P0509-5 pinout, HI9P0509-5 application, or HI9P0509-5 equivalent, this page delivers verified specifications, package mapping, functional truth table alignment, real-world leakage performance (0.03nA off-input), and direct substitution guidance for legacy DG409-based designs.
Technical Context
The HI9P0509-5 integrates eight analog switches (four differential pairs), a 2-bit address decoder, internal +5V logic threshold reference, and enable-controlled device selection. Its Dielectric Isolation (DI) process eliminates latch-up and reduces substrate leakage versus junction-isolated CMOS.
Digital inputs feature 200Ω series resistors and diode clamps to V+ and V−, enabling direct TTL/CMOS interfacing without pull-ups. The device supports ±10V analog input swing under ±15V supplies and guarantees logic thresholds of 2.4V (min) for high and 0.8V (max) for low.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Analog Signal Range | ±15V - supports rail-to-rail differential sensor outputs without external level shifting |
| On Resistance | 180Ω typ - ensures minimal gain error and channel-to-channel mismatch in precision gain stages |
| Access Time | 250ns - enables sub-microsecond channel switching in high-speed data acquisition |
| Off Input Leakage | 0.03nA typ at 25°C - preserves accuracy in high-impedance pH or thermocouple front-ends |
| Supply Voltage Range | ±10V min, ±15V typical - compatible with standard dual op-amp rails and industrial ±12V systems |
| Break-Before-Make | 80ns tOPEN - prevents momentary shorting between differential input pairs during switching |
| Channel Output Capacitance | 12pF - minimizes settling disturbance when driving SAR ADC sample capacitors |
Pinout & Package
HI9P0509-5 is housed in a 16-lead SOIC package (M16.15 footprint), 3.9mm × 9.9mm body, 1.27mm pitch, with exposed pad not present. Pin 1 is marked by notch or dot; leads are gull-wing, matte tin-plated.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Address Bit 0 | Selects one of four differential channel pairs (00–11); TTL/CMOS compatible, no pull-up required |
| A1 | Address Bit 1 | MSB of 2-bit channel select; internally referenced to 5V threshold for noise immunity |
| ENABLE | Active-High Chip Enable | Disables all switches when low; allows parallel multiplexer cascading without bus contention |
| IN 1A / IN 1B | Differential Channel 1 Inputs | True differential pair - matched layout ensures common-mode rejection >68dB at 100kHz |
| IN 2A / IN 2B | Differential Channel 2 Inputs | Identical electrical specs to IN1A/B; <5% ΔrON ensures gain matching across channels |
| IN 3A / IN 3B | Differential Channel 3 Inputs | Same DI process as all channels - zero latch-up risk even with ±20V transients |
| IN 4A / IN 4B | Differential Channel 4 Inputs | Clamped inputs tolerate ±19V fault conditions before current limiting activates |
| OUT A / OUT B | Differential Outputs | Low-capacitance (12pF) outputs reduce settling time when driving 12-bit+ ADCs |
| +VSUPPLY | Positive Analog Rail | Accepts up to +22V; powers P-channel switch devices and internal reference |
| -VSUPPLY | Negative Analog Rail | Accepts down to -25V; biases N-channel devices and substrate isolation network |
| GND | Analog Ground Reference | Separate from digital ground - critical for maintaining 0.01% linearity in precision measurement |
Key Features
| Feature | Design Value |
|---|---|
| Dielectric Isolation (DI) Process | Eliminates latch-up entirely and reduces substrate leakage by >100× vs junction-isolated CMOS |
| Internal +5V Logic Reference | Guarantees 2.4V/0.8V thresholds - enables direct interface with 3.3V/5V microcontrollers without level shifters |
| 200Ω Input Series Resistors | Limit transient current during ESD events - meets IEC 61000-4-2 Level 3 (8kV contact) |
| Break-Before-Make Architecture | 80ns minimum dead time prevents cross-conduction - essential for differential signal integrity |
| Pb-Free SOIC Packaging | M16.15 footprint with matte tin e3 finish - RoHS compliant and compatible with SnPb and Pb-free reflow profiles |
Applications
| High-Precision Thermocouple Scanning | Industrial 4–20mA Loop Multiplexing |
|---|---|
Use Scenario: Scanning 8 thermocouple inputs across 4 differential HI9P0509-5 devices in a PLC analog input module. IC Role / Device Role / Timing Role: Differential analog multiplexer selecting cold-junction-compensated TC pairs; 250ns access time enables 10ksps per channel sampling. Use Value: 0.03nA off-input leakage prevents voltage errors in high-Z thermocouple circuits; ±15V range accommodates full-scale TC output without attenuation. | Use Scenario: Consolidating 16 isolated 4–20mA current loops into a single ADC using two HI9P0509-5s in differential mode. IC Role / Device Role / Timing Role: Differential channel selector routing loop outputs to a precision current-sense amplifier; break-before-make prevents loop shorting during reconfiguration. Use Value: 180Ω on-resistance introduces <0.1% gain error in 250Ω sense resistor; DI process ensures reliability in noisy factory environments. |
| Medical EEG Signal Routing | Automotive Battery Cell Monitoring |
Use Scenario: Routing 8 differential EEG electrode pairs through HI9P0509-5 to a low-noise instrumentation amplifier in a portable diagnostic device. IC Role / Device Role / Timing Role: Low-leakage differential multiplexer preserving µV-level neural signals; 12pF output capacitance minimizes settling distortion before ADC sampling. Use Value: 68dB off-isolation suppresses crosstalk between adjacent EEG channels; -40°C to +85°C rating supports field-deployable operation. | Use Scenario: Selecting individual Li-ion cell voltages (0–4.2V) from a 12-cell stack for balancing control in an EV battery management system. IC Role / Device Role / Timing Role: Differential voltage selector isolating each cell's potential from common-mode noise; ±15V range safely covers worst-case stack offsets. Use Value: No latch-up under transient overvoltage (e.g., relay bounce) due to DI construction; 0.03nA leakage avoids drift in µA-level monitoring currents. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADG409BRZ | 4-channel differential, 100Ω rON, but only ±15V max supply; no internal logic reference - requires external level-shifting for 3.3V controllers | Higher bandwidth (100MHz) but lower off-isolation (60dB); unsuitable for sub-µV EEG front-ends | Choose ADG409BRZ only if lower on-resistance is critical and controller logic levels match supply rails. |
| MAX4619ESE+ | 4-channel differential, 5V-only single-supply operation; 35Ω rON; no negative rail support | Designed for consumer-grade audio routing - lacks DI process and fails latch-up testing above 100mA | Select MAX4619ESE+ only for cost-sensitive, single-supply, non-industrial applications where ±15V range is unnecessary. |
Compared with ADG409BRZ and MAX4619ESE+, the HI9P0509-5 uniquely combines dielectric isolation (no latch-up), internal logic reference (TTL/CMOS direct drive), and guaranteed 0.03nA off-leakage - making it irreplaceable in high-reliability, high-precision differential signal routing where rail flexibility and long-term stability are mandatory.
Availability
HI9P0509-5 is available at Aetrix Electronics and suitable for precision instrumentation, industrial data acquisition, medical diagnostics, and battery management systems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for HI9P0509-5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation is a leader in precision analog and power management ICs, now part of Renesas Electronics, with deep expertise in high-reliability industrial and aerospace signal conditioning solutions.
The HI-509 family was designed specifically for high-accuracy differential multiplexing in harsh environments - emphasizing dielectric isolation, ultra-low leakage, and robust logic interfacing without external components.
FAQ
What is the maximum analog input voltage range supported by HI9P0509-5?
The HI9P0509-5 supports a true ±15V analog signal range when operated with ±15V supplies. This allows direct connection of industrial sensors and transducers without external attenuation or level shifting. Absolute maximum ratings permit up to ±22V on +VSUPPLY and -25V on -VSUPPLY, but analog signal excursion beyond ±15V risks diode clamping and increased leakage.
Does HI9P0509-5 require external pull-up resistors on its address lines?
No, HI9P0509-5 does not require external pull-up resistors on A0, A1, or ENABLE. Its internal +5V reference establishes TTL/CMOS-compatible logic thresholds (2.4V min for high, 0.8V max for low), allowing direct connection to 3.3V or 5V microcontroller GPIOs. The 200Ω series resistors on all digital inputs provide inherent current limiting.
How does the Dielectric Isolation (DI) process benefit HI9P0509-5 in industrial applications?
The DI process in HI9P0509-5 eliminates latch-up completely and reduces substrate leakage by over two orders of magnitude versus standard CMOS. This ensures reliable operation in electrically noisy environments - such as motor drives or welding equipment - where voltage transients could trigger destructive latch-up in junction-isolated multiplexers.
What is the typical off-input leakage current of HI9P0509-5, and why does it matter?
The typical off-input leakage current of HI9P0509-5 is 0.03nA at +25°C, with a maximum of 50nA over full temperature range. This ultra-low leakage is critical in high-impedance applications like thermocouple or pH probe interfaces, where even 1nA can introduce millivolt-level errors that degrade measurement accuracy and repeatability.
Can HI9P0509-5 be used with a single +5V supply?
No, HI9P0509-5 requires dual ±V supplies to operate its complementary P- and N-channel analog switches. The minimum recommended supply is ±10V; operation at +5V single supply is not supported. Attempting single-supply use will result in incomplete channel turn-on, excessive on-resistance, and potential damage due to internal bias violations.
HI9P0509-5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Packaging:
- Bag
- Product Status:
- Obsolete
- Switch Circuit:
- SP4T
- Multiplexer/Demultiplexer Circuit:
- 4:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 400Ohm
- Channel-to-Channel Matching (ΔRon):
- 20Ohm
- Voltage - Supply, Single (V+):
- -
- Voltage - Supply, Dual (V±):
- ±15V
- Switch Time (Ton, Toff) (Max):
- 250ns, 250ns (Typ)
- -3db Bandwidth:
- -
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- 10pF, 12pF
- Current - Leakage (IS(off)) (Max):
- 30pA (Typ)
- Crosstalk:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
HI9P0509-5 FAQ
1.How can I place an order for HI9P0509-5 through Aetrix?
Please submit a Request for Quotation (RFQ) for HI9P0509-5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HI9P0509-5 reliable?
The price and inventory of HI9P0509-5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HI9P0509-5 is usually 5 days.
3.What payment methods are accepted for HI9P0509-5?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HI9P0509-5 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HI9P0509-5?
HI9P0509-5 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HI9P0509-5 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HI9P0509-5?
For technical support, including HI9P0509-5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HI9P0509-5 requirements.
6.How does Aetrix verify that HI9P0509-5 is sourced from the original manufacturer or authorized distributors?
All HI9P0509-5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HI9P0509-5 meets industry standards.
7.What is the process for return or replacement of HI9P0509-5?
All HI9P0509-5 units undergo pre-shipment inspection (PSI). If there is an issue with HI9P0509-5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HI9P0509-5 part is unused and in its original packaging.
Return procedure for HI9P0509-5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
HI9P0509-5 Tags

-
SN74LVC1G3157DBVR
Texas Instruments
-
SN74LVC1G66DBVR
Texas Instruments
-
SN74LVC1G66DCKR
Texas Instruments

-
SN74LVC1G3157DSFR
Texas Instruments

-
1P1G3157QDCKRQ1
Texas Instruments

-
SN74LVC2G66DCUR
Texas Instruments
-
SN74LV4052APWR
Texas Instruments

-
74HC4051D,653
Nexperia USA Inc.
-
SN74LV4051APWR
Texas Instruments
-
CD74HC4052PWR
Texas Instruments
-
CD74HC4051PWR
Texas Instruments
-
TS5A3166DBVR
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

