Renesas HI9P5043-5Z
- Part No.:
- HI9P5043-5Z
- Manufacturer:
- Renesas
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
HI9P5043-5Z.pdf
- Description:
- IC SWITCH SPDT X 2 75OHM 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:519
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
HI9P5043-5Z from Intersil is a dual SPDT CMOS analog switch optimized for ±15V signal routing in precision instrumentation and data acquisition systems, featuring 50Ω on-resistance, 80mA peak current handling, break-before-make switching, and 370ns turn-on time. It operates from 0°C to 75°C in a Pb-free 16-lead SOIC package.
For engineers reviewing the HI9P5043-5Z datasheet, HI9P5043-5Z pinout, HI9P5043-5Z application, or HI9P5043-5Z equivalent, key selection criteria include analog signal range (±15V), channel matching (≤10Ω ΔrON), low leakage (0.8nA at 25°C), and TTL/CMOS logic compatibility - critical for multiplexed sensor interfaces and programmable gain amplifier designs.
Technical Context
The HI9P5043-5Z implements two independent SPDT switches using dielectric-isolated CMOS process technology, enabling latch-free operation and ultra-low input/output leakage. Each switch supports rail-to-rail analog signals up to ±15V with constant rON across voltage and temperature.
It uses separate digital control inputs (A1, A2) per switch, supports break-before-make timing to prevent signal shorting, and integrates level-shifting buffers compatible with TTL, CMOS, DTL, and PMOS logic families - eliminating external interface circuitry in mixed-signal systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Analog Signal Range | ±15V - supports full-rail signal switching without clipping in bipolar op-amp and ADC/DAC interface circuits |
| ON Resistance (rON) | 50Ω typical - ensures minimal insertion loss and gain error in precision analog paths |
| Channel Match (ΔrON) | ≤10Ω max - maintains consistent gain and phase response across dual channels in differential or switched-gain applications |
| Switching Speed | tON = 370ns, tOFF = 280ns - enables high-frequency multiplexing up to ~1MHz without significant settling distortion |
| Leakage Current | 0.8nA at 25°C - preserves accuracy in high-impedance sample-and-hold and sensor front-end circuits |
| Power Dissipation | 1.5mW at 25°C - allows dense integration in thermally constrained industrial modules |
| Digital Input Compatibility | TTL/CMOS/DTL/PMOS - simplifies direct interfacing with microcontrollers, FPGAs, and legacy logic without level shifters |
Pinout & Package
HI9P5043-5Z is housed in a 16-lead narrow-body SOIC package (JEDEC MS-012-AC, M16.15), 3.9mm × 9.9mm footprint, 1.27mm lead pitch, RoHS-compliant matte tin finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 7, 8 | Switch Source/Drain Terminals (S1, D1, S2, D2, S3, D3, S4, D4) | Four independent analog path terminals for dual SPDT configuration; unused pins must be grounded per datasheet |
| 6, 15 | Digital Control Inputs (A1, A2) | Active-high logic inputs controlling respective SPDT switches; TTL/CMOS compatible thresholds (VAL = 0.8V, VAH = 2.4V) |
| 9, 10 | Logic Supply Pins (VL, VR) | VL powers internal level shifters (typically +5V); VR is reference ground for logic interface - decoupling required |
| 11, 12 | Analog Supplies (V+, V−) | Supports ±15V analog rails; must be bypassed with low-ESR capacitors to minimize switching transients |
| 13, 14, 16 | Ground / Unused Pins | Pin 13 = GND; pins 14 & 16 are internally connected and must be grounded to prevent noise coupling |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail analog switching | Operates with signals from V− to V+ (±15V), enabling direct connection to op-amps and ADCs without level shifting |
| Break-before-make timing | Guarantees no overlap between switch states, preventing momentary shorts in gain-switching or filter-selection circuits |
| Dielectric isolation process | Eliminates latch-up risk and reduces leakage to 0.8nA - essential for high-Z medical and test equipment inputs |
| Pb-free SOIC packaging | RoHS-compliant matte tin termination, qualified for reflow soldering per IPC/JEDEC J-STD-020 at peak 260°C |
| Low power consumption | 1.5mW quiescent dissipation minimizes self-heating drift in precision measurement systems |
Applications
| Instrumentation Multiplexer | Programmable Gain Amplifier |
|---|---|
|
Use Scenario: Selecting among multiple sensor inputs (thermocouples, strain gauges) feeding a single precision ADC in an industrial PLC. IC Role / Device Role / Timing Role: Dual SPDT switch routes analog signals while maintaining matched channel resistance and low leakage. Use Value: 50Ω rON and ≤10Ω ΔrON ensure consistent gain scaling; ±15V range accommodates unconditioned sensor outputs. |
Use Scenario: Configuring feedback resistor networks in a digitally controlled op-amp stage for variable gain (1×, 10×, 100×). IC Role / Device Role / Timing Role: HI9P5043-5Z acts as low-distortion analog switch in the feedback loop, toggled by MCU GPIOs. Use Value: 370ns tON enables fast gain changes without transient overshoot; 0.8nA leakage prevents DC offset accumulation. |
| Sample-and-Hold Circuit | Digital Filter Switching |
|
Use Scenario: Capturing fast transient waveforms in oscilloscope front-ends where hold capacitor charging must be isolated from source impedance. IC Role / Device Role / Timing Role: HI9P5043-5Z connects/disconnects input signal to sampling capacitor with precise timing control. Use Value: Low charge injection (5mV typical) minimizes sampling pedestal error; break-before-make prevents hold capacitor discharge. |
Use Scenario: Reconfiguring RC time constants in switched-capacitor or active filter stages for adaptive bandwidth control. IC Role / Device Role / Timing Role: Dual SPDT selects between discrete resistor networks to alter cutoff frequency in real time. Use Value: 50Ω rON introduces negligible error in time-constant calculation; 80mA current rating handles filter bias currents safely. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HI9P5043-5 | Same electrical specs and pinout, but SnPb (non-RoHS) terminations | Not suitable for new RoHS-compliant designs; requires lead-free assembly process validation | Select HI9P5043-5Z for all new production requiring Pb-free compliance and reflow compatibility. |
| HI3-5043-5Z | Identical function and specs, but in 16-lead PDIP (E16.3) instead of SOIC | Used in through-hole prototyping or legacy wave-soldered boards; not reflow-compatible | Choose HI9P5043-5Z for surface-mount volume production; HI3-5043-5Z only for hand-soldered or wave-soldered assemblies. |
Compared with HI9P5043-5 and HI3-5043-5Z, the HI9P5043-5Z provides identical analog performance in a RoHS-compliant, reflow-solderable SOIC package - making it the preferred choice for modern automated PCB assembly while preserving drop-in functionality in existing HI9P5043-5 layouts.
Availability
HI9P5043-5Z is available at Aetrix Electronics and suitable for industrial instrumentation, test equipment, and programmable analog front-ends requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for HI9P5043-5Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation is a leader in precision analog and power management ICs, serving industrial, infrastructure, and high-end consumer markets with high-reliability, low-drift solutions.
The HI-504X series was designed specifically for high-fidelity analog signal routing in demanding environments - emphasizing rail-to-rail operation, low leakage, and latch-free robustness for test, measurement, and control systems.
FAQ
What is the maximum analog signal voltage supported by HI9P5043-5Z?
The HI9P5043-5Z supports analog signals from V− to V+, with absolute maximum supply voltage of ±15V - enabling true rail-to-rail switching across the full ±15V range. This allows direct interfacing with bipolar op-amps and unconditioned sensor outputs without external level shifting, and is confirmed in the Absolute Maximum Ratings table (Page 5) and Electrical Specifications (Page 5).
Does HI9P5043-5Z require external pull-up resistors on its digital control inputs?
No, HI9P5043-5Z does not require external pull-up resistors. Its digital inputs (A1, A2) have TTL/CMOS-compatible thresholds (VAL = 0.8V, VAH = 2.4V) and internal input structures that accept direct drive from microcontrollers or logic gates. The datasheet specifies input leakage of ≤1.0μA, confirming robust noise immunity without external biasing.
Can HI9P5043-5Z be used in a ±12V system?
Yes, HI9P5043-5Z is fully functional in ±12V systems. Its analog signal range (±15V) and supply voltage rating (36V total) encompass ±12V operation. Performance parameters including rON (50Ω), leakage (0.8nA), and switching times (370ns/280ns) are guaranteed across the full operating range, and Figure 1B confirms stable rON down to ±10V supplies.
What is the thermal resistance (θJA) of the HI9P5043-5Z SOIC package?
The HI9P5043-5Z in its 16-lead SOIC package has a typical junction-to-ambient thermal resistance (θJA) of 110°C/W, as specified in the Thermal Information table (Page 5). This value assumes mounting on a standard evaluation PCB in free air and informs thermal design for continuous 80mA operation or high-duty-cycle switching.
Is HI9P5043-5Z pin-compatible with the older HI-5043 family in CERDIP packages?
Yes, HI9P5043-5Z is functionally and pinout-compatible with HI-5043 variants in CERDIP (e.g., HI1-5043-5) and PDIP (e.g., HI3-5043-5Z), as confirmed by identical pin numbering, terminal functions, and dual SPDT topology in the Pinouts section (Pages 2–3). However, package dimensions and soldering profiles differ - SOIC requires reflow, while CERDIP/PDIP may use wave or hand-soldering.
HI9P5043-5Z Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Active
- Switch Circuit:
- SPDT
- Multiplexer/Demultiplexer Circuit:
- 2:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 75Ohm
- Channel-to-Channel Matching (ΔRon):
- 2Ohm
- Voltage - Supply, Single (V+):
- -
- Voltage - Supply, Dual (V±):
- ±15V
- Switch Time (Ton, Toff) (Max):
- 500ns, 500ns
- -3db Bandwidth:
- -
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- 11pF, 11pF
- Current - Leakage (IS(off)) (Max):
- 2nA
- Crosstalk:
- -88dB @ 100kHz
- Operating Temperature:
- 0°C ~ 75°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
HI9P5043-5Z FAQ
1.How can I place an order for HI9P5043-5Z through Aetrix?
Please submit a Request for Quotation (RFQ) for HI9P5043-5Z on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HI9P5043-5Z reliable?
The price and inventory of HI9P5043-5Z are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HI9P5043-5Z is usually 5 days.
3.What payment methods are accepted for HI9P5043-5Z?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HI9P5043-5Z transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HI9P5043-5Z?
HI9P5043-5Z orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HI9P5043-5Z order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HI9P5043-5Z?
For technical support, including HI9P5043-5Z datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HI9P5043-5Z requirements.
6.How does Aetrix verify that HI9P5043-5Z is sourced from the original manufacturer or authorized distributors?
All HI9P5043-5Z products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HI9P5043-5Z meets industry standards.
7.What is the process for return or replacement of HI9P5043-5Z?
All HI9P5043-5Z units undergo pre-shipment inspection (PSI). If there is an issue with HI9P5043-5Z, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HI9P5043-5Z part is unused and in its original packaging.
Return procedure for HI9P5043-5Z:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
HI9P5043-5Z Tags

-
SN74LVC1G3157DBVR
Texas Instruments
-
SN74LVC1G66DBVR
Texas Instruments
-
SN74LVC1G66DCKR
Texas Instruments

-
SN74LVC1G3157DSFR
Texas Instruments

-
1P1G3157QDCKRQ1
Texas Instruments

-
SN74LVC2G66DCUR
Texas Instruments
-
SN74LV4052APWR
Texas Instruments

-
74HC4051D,653
Nexperia USA Inc.
-
SN74LV4051APWR
Texas Instruments
-
CD74HC4052PWR
Texas Instruments
-
CD74HC4051PWR
Texas Instruments
-
TS5A3166DBVR
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

