My Inquiry
My Account
Renesas HIP6004BCRZ-T
- Part No.:
- HIP6004BCRZ-T
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 20-VQFN Exposed Pad
- Datasheet:
-
HIP6004BCRZ-T.pdf
- Description:
- IC REG CTRLR INTEL 1OUT 20QFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,529
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
HIP6004BCRZ-T from Intersil is a synchronous-rectified buck PWM controller with integrated voltage-mode regulation, 5-bit VID DAC, and output voltage monitoring for microprocessor power supplies. It drives two N-channel MOSFETs, supports 1.3V–3.5V output via TTL-compatible VID inputs, delivers ±1% output regulation over temperature and line, and operates at 200kHz (adjustable 50kHz–1MHz) with 0%–100% duty cycle control.
For engineers reviewing the HIP6004BCRZ-T datasheet, HIP6004BCRZ-T pinout, HIP6004BCRZ-T application, or HIP6004BCRZ-T equivalent, key selection considerations include its QFN-20 package, rDS(ON)-based overcurrent sensing, VSEN/PGOOD/OVP monitoring architecture, and compatibility with Pentium®/PowerPC™/K6™ CPU core voltage regulation requirements.
Technical Context
The HIP6004BCRZ-T implements voltage-mode PWM control using a 200kHz free-running oscillator (programmable via RT resistor), a 15MHz gain-bandwidth error amplifier with 6V/µs slew rate, and a precision internal reference tracked by a 5-bit DAC. Its feedback loop uses COMP (error amp output) and FB (inverting input) pins for external compensation.
Overcurrent protection relies on sensing the upper MOSFET's rDS(ON) via OCSET and PHASE pins-eliminating external current-sense resistors-while overvoltage protection triggers OVP pin sourcing (60mA) to drive an external SCR. Power-good status is generated by a window comparator tracking DACOUT with ±10% threshold and 2% hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Topology | Synchronous-rectified buck PWM controller for CPU core voltage regulation |
| Output Voltage Range | 1.3V–3.5V in 0.05V steps (1.3–2.05V) and 0.1V steps (2.1–3.5V) via VID0–VID4 |
| Regulation Accuracy | ±1% over temperature and line voltage variations-enables stable microprocessor operation |
| Switching Frequency | 200kHz nominal; adjustable from <50kHz to >1MHz via RT resistor-supports layout-optimized EMI control |
| Error Amplifier GBW | 15MHz gain-bandwidth product with 6V/µs slew rate-enables fast transient response to CPU load steps |
| Overcurrent Sensing | rDS(ON)-based, no external sense resistor required-reduces BOM cost and PCB area |
| Package | 20-pin 5×5 mm QFN (JEDEC MO-220 L20.5x5)-near chip-scale footprint with exposed thermal pad |
Pinout & Package
Package: 20-lead 5×5 mm QFN (JEDEC MO-220 L20.5x5) with exposed thermal pad; RoHS-compliant Pb-free termination.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VSEN (1) | Output voltage sense input | Connects directly to regulated output; feeds PGOOD and OVP comparators |
| OCSET (2) | Overcurrent threshold programming | Internal 200µA current source + external ROCSET sets IPEAK trip point using rDS(ON) |
| SS (3) | Soft-start timing node | 10µA internal current charges external CSS capacitor to control startup ramp rate |
| VID0–VID4 (4–8) | DAC digital inputs | TTL-compatible 5-bit bus selects DACOUT voltage (1.3–3.5V) and sets PGOOD/OVP thresholds |
| COMP (9) | Error amplifier output | Drives external compensation network; connects to PWM comparator input |
| FB (10) | Error amplifier inverting input | Connects to output divider; forms closed-loop voltage regulation path |
| GND (11) | Signal ground reference | Reference for all analog circuitry; separate from PGND to minimize noise coupling |
| PGOOD (12) | Open-drain power-good indicator | Pulled low when VSEN is outside ±10% of DACOUT; high during disable ('11111' VID) |
| PHASE (13) | High-side MOSFET source monitor | Provides return path for UGATE drive and rDS(ON) voltage sensing for OC protection |
| UGATE (14) | Upper gate driver output | Source/sink capable (350/500mA typ); drives N-MOSFET gate via BOOT bootstrap |
| BOOT (15) | Bootstrap supply for UGATE | Charged via external diode/capacitor to provide >VPHASE gate drive voltage |
| PGND (16) | Power ground return | Low-impedance return for lower MOSFET source and power-stage currents |
| LGATE (17) | Lower gate driver output | Source/sink capable (300/450mA typ); drives N-MOSFET gate referenced to PGND |
| VCC (18) | Bias supply input | Accepts +12V ±10%; powers internal logic, drivers, and amplifiers |
| OVP (19) | Overvoltage fault output | Active-high 60mA sink/source; triggers external SCR crowbar on >115% DACOUT |
| RT (20) | Oscillator frequency set | Resistor to GND increases frequency; resistor to VCC decreases frequency per datasheet equations |
Key Features
| Feature | Design Value |
|---|---|
| VID-programmable output | 32 discrete voltages from 1.3V to 3.5V with binary step resolution-enables dynamic CPU voltage scaling |
| Voltage-mode control | Single-loop architecture with 15MHz error amplifier-simplifies compensation design vs current-mode |
| rDS(ON) current sensing | Eliminates external sense resistor-reduces power loss, BOM count, and board space |
| Integrated protection suite | Programmable overcurrent, overvoltage (OVP pin), and power-good monitoring-replaces discrete supervisor ICs |
| QFN thermal performance | θJA = 33°C/W (QFN) vs 65°C/W (SOIC)-enables higher power density in compact CPU VRMs |
Applications
| Desktop CPU Core Power Supply | Laptop CPU Voltage Regulator |
|---|---|
Use Scenario: Providing tightly regulated core voltage to Intel Pentium II or AMD K6 microprocessors during dynamic frequency scaling. IC Role / Device Role / Timing Role: Primary PWM controller managing synchronous buck conversion, VID decoding, and real-time output monitoring. Use Value: ±1% regulation accuracy and 0%–100% duty cycle ensure stable operation across 1.3V–2.05V CPU VDD ranges under rapid load transients. | Use Scenario: Generating low-noise 1.8V–2.5V core supply for PowerPC™ embedded processors in portable industrial controllers. IC Role / Device Role / Timing Role: Central voltage-mode controller coordinating gate drive timing, soft-start sequencing, and PGOOD assertion for system boot validation. Use Value: Integrated SS pin with 10µA current source enables precise 5–20ms startup ramp-prevents inrush current damage to downstream logic. |
| Server Processor VRM | Legacy Workstation Power |
Use Scenario: High-current DC-DC stage in Alpha™ processor power delivery network requiring hiccup-mode overcurrent recovery. IC Role / Device Role / Timing Role: Fault-tolerant controller implementing rDS(ON)-based OC detection and automatic soft-start restart on overload. Use Value: OCSET/PHASE interface allows programmable trip thresholds independent of load current-supports wide MOSFET selection without redesign. | Use Scenario: Replacement power solution for aging 6X86™-based industrial PCs needing 3.3V core rail with legacy VID compatibility. IC Role / Device Role / Timing Role: Drop-in controller supporting standard 5-bit VID protocol and generating PGOOD for motherboard reset logic. Use Value: TTL-compatible VID inputs and ±10% PGOOD window match original system timing specifications-no firmware or hardware changes required. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HIP6006BCRZ-T | Same pinout, enhanced 1.2V–3.5V VID range, improved thermal resistance (θJA = 28°C/W), and tighter ±0.8% regulation | Supports newer low-voltage CPUs (e.g., Pentium III) requiring sub-1.5V operation | Select for new designs targeting extended VID range and better thermal performance |
| ISL6522CBZ-T | Different pinout (24-QFN), dual-phase capability, integrated MOSFET drivers with 1.2A peak current, and 0.5% regulation | Designed for multi-phase VRMs in high-end desktop/server platforms | Choose only if multi-phase topology and higher gate drive current are required |
Compared with HIP6004BCRZ-T, HIP6006BCRZ-T offers broader VID coverage and superior thermal metrics in identical QFN-20 packaging, while ISL6522CBZ-T provides multi-phase scalability at the cost of pinout incompatibility and increased complexity-making HIP6004BCRZ-T optimal for single-phase, cost-sensitive CPU VRMs.
Availability
HIP6004BCRZ-T is available at Aetrix Electronics and suitable for desktop CPU power supplies, laptop voltage regulators, and legacy workstation VRMs requiring stable component supply and long-term lifecycle support.
Supply support for HIP6004BCRZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation was a U.S.-based semiconductor company specializing in power management, precision analog, and interface ICs before its acquisition by Renesas Electronics in 2017.
The HIP6004B product line was designed specifically for single-phase synchronous buck regulation in high-performance microprocessor power supplies-including Pentium®, PowerPC™, and Alpha™ platforms-with emphasis on VID compatibility, thermal efficiency, and integrated protection.
FAQ
What is the recommended input voltage range for HIP6004BCRZ-T?
The HIP6004BCRZ-T is specified for a +12V ±10% bias supply on the VCC pin, and it supports converter input voltages of +5V or +12V as noted in the datasheet. The OCSET pin monitors VIN through the upper MOSFET's rDS(ON), so the actual input rail must be compatible with the selected MOSFET's voltage rating and the HIP6004BCRZ-T's absolute maximum ratings (VCC ≤ +15V). Operation outside these ranges risks permanent damage.
Does HIP6004BCRZ-T support 0% to 100% duty cycle operation?
Yes, the HIP6004BCRZ-T supports full 0% to 100% PWM duty cycle control, enabling deep dropout operation and seamless transitions between active and low-power states. This capability is explicitly stated in the datasheet and enabled by its voltage-mode architecture and high-bandwidth error amplifier-critical for maintaining regulation during CPU sleep-state transitions where output voltage must remain stable even at near-zero load.
How does overcurrent protection work in HIP6004BCRZ-T without a sense resistor?
The HIP6004BCRZ-T implements rDS(ON)-based overcurrent protection using the OCSET and PHASE pins. An internal 200µA current source develops a voltage across an external ROCSET resistor, which is compared to the voltage drop across the upper MOSFET's rDS(ON) sensed at PHASE. When the latter exceeds the former, the controller initiates hiccup-mode soft-start recovery. This eliminates the need for a discrete current-sense resistor, reducing power loss and board area in the HIP6004BCRZ-T design.
What is the function of the '11111' VID code on HIP6004BCRZ-T?
The '11111' VID code (all five VID pins high) disables the HIP6004BCRZ-T gate drivers and forces 0V output, activating the Power-On Reset function. Uniquely, PGOOD asserts high in this state-unlike normal operation-allowing AND-ing of PGOOD signals in dual-CPU systems. This behavior is documented in the datasheet and ensures safe initialization sequencing without requiring external logic to manage reset coordination between processors.
Is HIP6004BCRZ-T still recommended for new designs?
No, the HIP6004BCRZ-T is marked "NOT RECOMMENDED FOR NEW DESIGNS" in the official Intersil datasheet (FN4567 Rev 3.00). While fully functional and supported for legacy repair and continuity, Intersil provided no recommended replacement and advised contacting Technical Support for migration guidance. Aetrix Electronics maintains inventory for ongoing production of existing platforms but recommends evaluating HIP6006BCRZ-T for new implementations requiring similar functionality.
HIP6004BCRZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 20-VQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Controller, Intel Pentium®, II, Pro
- Voltage - Input:
- 5V, 12V
- Number of Outputs:
- 1
- Voltage - Output:
- 1.3V ~ 3.5V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-QFN (5x5)
HIP6004BCRZ-T FAQ
1.How can I place an order for HIP6004BCRZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for HIP6004BCRZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HIP6004BCRZ-T reliable?
The price and inventory of HIP6004BCRZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HIP6004BCRZ-T is usually 5 days.
3.What payment methods are accepted for HIP6004BCRZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HIP6004BCRZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HIP6004BCRZ-T?
HIP6004BCRZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HIP6004BCRZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HIP6004BCRZ-T?
For technical support, including HIP6004BCRZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HIP6004BCRZ-T requirements.
6.How does Aetrix verify that HIP6004BCRZ-T is sourced from the original manufacturer or authorized distributors?
All HIP6004BCRZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HIP6004BCRZ-T meets industry standards.
7.What is the process for return or replacement of HIP6004BCRZ-T?
All HIP6004BCRZ-T units undergo pre-shipment inspection (PSI). If there is an issue with HIP6004BCRZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HIP6004BCRZ-T part is unused and in its original packaging.
Return procedure for HIP6004BCRZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
HIP6004BCRZ-T Tags
-
TPS51206DSQR
Texas Instruments
-
TPS51200DRCR
Texas Instruments
-
TPS51200DRCT
Texas Instruments
-
TPS62740DSSR
Texas Instruments
-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi
-
RT9026GSP
Richtek USA Inc.
-
LP2998MRX/NOPB
Texas Instruments
-
TPS51200QDRCRQ1
Texas Instruments
-
DPA423GN-TL
Power Integrations
-
LM10011SD/NOPB
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
