Renesas HIP6004BCVZ
- Part No.:
- HIP6004BCVZ
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
HIP6004BCVZ.pdf
- Description:
- IC REG CTRLR INTEL 1OUT 20TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,174
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Product details
Overview
HIP6004BCVZ from Intersil is a synchronous-rectified buck PWM controller IC designed to drive two N-channel MOSFETs in high-performance microprocessor power supplies. It delivers precise output voltage regulation (±1% over line/temperature), supports 1.3V–3.5V DAC-programmable output via five VID pins, and integrates voltage-mode control with 15MHz gain-bandwidth error amplifier for fast transient response in Pentium® and PowerPC™ applications.
For engineers reviewing the HIP6004BCVZ datasheet, HIP6004BCVZ pinout, HIP6004BCVZ application, or HIP6004BCVZ equivalent, this page provides verified technical context, confirmed pin functions, real-world design meaning of key specs, and validated alternative options for legacy microprocessor VRM designs.
Technical Context
The HIP6004BCVZ implements voltage-mode PWM control using a 200kHz free-running oscillator adjustable from 50kHz to >1MHz via RT resistor. Its error amplifier delivers 15MHz gain-bandwidth and 6V/µs slew rate to support high-loop bandwidth for rapid load transients in CPU core supplies.
Overcurrent protection uses the upper MOSFET's rDS(ON)-not an external sense resistor-with OCSET pin current source (200µA typ.) and programmable trip threshold. Output voltage monitoring employs a window comparator tracking DACOUT to assert PGOOD within ±10% and trigger OVP at +115% DACOUT.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage Range | 1.3V–3.5V in 0.05V steps (1.3–2.05V) and 0.1V steps (2.1–3.5V) via 5-bit TTL DAC; sets both regulation target and PGOOD/OVP thresholds |
| Oscillator Frequency | 200kHz nominal (185–215kHz typ.), adjustable from <50kHz to >1MHz using RT resistor; enables optimization of efficiency vs. size in VRM designs |
| Error Amplifier GBW | 15MHz gain-bandwidth product with 6V/µs slew rate; supports >100kHz closed-loop bandwidth for sub-µs transient recovery in microprocessor loads |
| Voltage Regulation Accuracy | ±1% over line voltage and temperature; ensures stable core voltage under varying input and thermal conditions without external trimming |
| Power-Good Window | ±10% of DACOUT with 2% hysteresis; provides reliable sequencing signal for CPU reset and system enable logic |
| OC Protection Method | rDS(ON)-based sensing via OCSET pin (200µA current source); eliminates sense resistor, reduces BOM cost and PCB area, improves efficiency |
| Supply Voltage | +12V ±10% on VCC pin; compatible with standard ATX 12V rail; no +5V bias required for operation |
Pinout & Package
HIP6004BCVZ is packaged in a 20-lead TSSOP (Moisture Sensitivity Level 1, Pb-free per RoHS). The package footprint complies with JEDEC MO-220 standard and supports fine-pitch surface-mount assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VSEN (1) | Output voltage feedback input | Direct connection to converter output; feeds PGOOD and OVP comparators-no external divider needed for DAC-tracked monitoring |
| OCSET (2) | Overcurrent threshold programming | Connects to upper MOSFET drain via ROCSET; sets IPEAK trip point using internal 200µA current source and rDS(ON) |
| SS (3) | Soft-start timing node | Internal 10µA current charges external CSS capacitor; controls ramp-up time and prevents inrush current during startup |
| VID0–VID4 (4–8) | DAC digital inputs | TTL-compatible 5-bit bus; selects one of 32 discrete DACOUT voltages (1.3–3.5V) that define output setpoint and protection thresholds |
| COMP (9) | Error amplifier output | Drives external compensation network; connects to FB through RC network to stabilize voltage-mode loop |
| FB (10) | Error amplifier inverting input | Connected to VSEN; forms feedback node for regulation loop-no internal resistor divider required |
| GND (11) | Signal ground reference | Reference for all analog circuitry; must be low-impedance connection to minimize noise coupling into sensitive nodes |
| PGOOD (12) | Open-drain status output | Pulled low when VSEN is outside ±10% of DACOUT; '11111' VID disables regulator but asserts high PGOOD for dual-CPU systems |
| PHASE (13) | High-side switch source monitor | Connects to upper MOSFET source; provides return path for UGATE drive and voltage reference for rDS(ON)-based OC detection |
| UGATE (14) | Upper MOSFET gate driver output | Source/sink capable (500mA/5.5Ω typ.); drives N-channel high-side FET with bootstrap supply from BOOT pin |
| BOOT (15) | Bootstrap supply input | Accepts charge from external bootstrap capacitor; generates floating bias for UGATE to fully enhance N-channel high-side FET |
| PGND (16) | Power ground return | Low-inductance tie point for lower MOSFET source and bulk output capacitors; separates power and signal grounds |
| LGATE (17) | Lower MOSFET gate driver output | Source/sink capable (450mA/3.5Ω typ.); directly drives N-channel synchronous rectifier with minimal dead-time requirements |
| VCC (18) | Bias supply input | Accepts +12V ±10%; powers internal logic, drivers, and references-no LDO or external regulator needed |
| OVP (19) | External crowbar trigger | Active-high output that drives external SCR during >+115% overvoltage; disables PWM and protects downstream components |
| RT (20) | Oscillator frequency adjust | Resistor-to-GND increases frequency (Fs ≈ 200kHz + 5×10⁶/RT); resistor-to-VCC decreases frequency (Fs ≈ 200kHz – 4×10⁷/RT) |
Key Features
| Feature | Design Value |
|---|---|
| Integrated 5-bit TTL DAC | Enables software-controlled output voltage selection across 32 discrete levels (1.3–3.5V) without external DAC or EEPROM |
| rDS(ON)-based overcurrent sensing | Eliminates current-sense resistor, reducing component count, board space, and conduction losses in high-current CPU rails |
| Voltage-mode PWM architecture | Simplifies loop compensation versus current-mode; supports single-pole dominant design with predictable phase margin |
| Full 0–100% duty cycle range | Permits operation down to very low output voltages (e.g., 1.3V) from 12V input without duty-cycle limiting artifacts |
| Programmable oscillator (50kHz–1MHz) | Allows trade-off between magnetic component size (higher fSW) and switching loss (lower fSW) for optimal VRM efficiency |
Applications
| Desktop CPU Core Supply | Laptop Processor VRM |
|---|---|
Use Scenario: Regulating core voltage for Intel Pentium II or AMD K6 microprocessors requiring dynamic VID-based voltage scaling. IC Role / Device Role / Timing Role: Primary PWM controller managing synchronous buck topology, DAC-based VID interface, and real-time overvoltage/overcurrent protection. Use Value: Enables precise ±1% output regulation across temperature and line variations while supporting fast load transients up to 1A/ns typical of desktop CPUs. | Use Scenario: Providing tightly regulated 1.8V–2.5V supply to mobile PowerPC or Alpha processors in space-constrained laptop motherboards. IC Role / Device Role / Timing Role: Synchronous buck controller with integrated soft-start, PGOOD signaling, and rDS(ON) current sensing to reduce BOM count and thermal footprint. Use Value: Delivers stable core voltage with <5ms soft-start and ±10% PGOOD window-critical for reliable boot sequencing in portable systems. |
| Embedded x86 System Power | Legacy Industrial Controller Supply |
Use Scenario: Powering embedded Pentium Pro or 6x86-based industrial controllers where long-term component availability and proven reliability are mandatory. IC Role / Device Role / Timing Role: Fixed-frequency voltage-mode controller with 200kHz base switching and external RT adjustment for EMI tuning. Use Value: Provides deterministic transient response and robust fault handling (hiccup-mode OC, crowbar OVP) in mission-critical control environments. | Use Scenario: Generating 3.3V or 2.5V auxiliary rails in programmable logic controllers (PLCs) using legacy 12V backplane distribution. IC Role / Device Role / Timing Role: High-efficiency synchronous buck controller replacing linear regulators or older multi-chip VRM solutions. Use Value: Achieves >90% efficiency at 10A loads while maintaining ±1% regulation-reducing heat sink requirements and improving system MTBF. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6522CBZ | Single-phase controller with integrated MOSFET drivers, 0.6V–5.5V output range, 300kHz–1.5MHz programmable frequency, and digital VID interface compliant with Intel VRM 9.0/10.0. | Designed for newer Pentium 4 and Xeon platforms with tighter voltage tolerances (±0.8%) and faster transient response requirements. | Select ISL6522CBZ only if upgrading to VRM 9.0+ compliance and requiring higher frequency operation (>300kHz) with improved light-load efficiency. |
| TPS51020PWR | Single-phase controller with adaptive on-time D-CAP control, 0.7V–5.5V output, integrated 5-bit VID, and 300kHz–1MHz frequency range; supports ceramic output capacitors without external compensation. | Targeted at DDR memory and chipset rails with fast transient demands; lacks rDS(ON) OC sensing-requires external current sense resistor. | Choose TPS51020PWR for new designs needing simplified layout and reduced component count where rDS(ON) sensing is not required and VRM 10.1 compliance is needed. |
Compared with HIP6004BCVZ, ISL6522CBZ offers higher frequency flexibility and VRM 9.0 compliance but requires updated VID timing and tighter tolerance components; TPS51020PWR provides adaptive control for better transient response but sacrifices the rDS(ON) OC sensing advantage and adds a current-sense resistor.
Availability
HIP6004BCVZ is available at Aetrix Electronics and suitable for legacy microprocessor power supplies, industrial embedded controllers, and Pentium-class VRM replacements requiring stable component supply and long-lifecycle support.
Supply support for HIP6004BCVZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation (now part of Renesas Electronics) is a U.S.-based semiconductor company specializing in precision analog, power management, and interface ICs for computing, industrial, and communications markets.
The HIP6004B family was developed specifically for synchronous-buck VRM applications in high-performance x86 and RISC microprocessors, emphasizing integration, accuracy, and robust protection in compact TSSOP and QFN packages.
FAQ
What is the operating temperature range for the HIP6004BCVZ?
The HIP6004BCVZ is rated for an ambient temperature range of 0°C to +70°C, as specified in the Intersil FN4567 datasheet. This commercial-grade rating aligns with its intended use in desktop and embedded microprocessor power supplies where airflow and thermal management are controlled. The device's maximum junction temperature is 150°C, and thermal resistance θJA for the TSSOP package is 85°C/W under standard test conditions.
Does the HIP6004BCVZ require an external current-sense resistor for overcurrent protection?
No, the HIP6004BCVZ does not require an external current-sense resistor. It implements overcurrent protection using the rDS(ON) of the upper N-channel MOSFET, with the OCSET pin sourcing a precise 200µA current to set the trip threshold via an external resistor (ROCSET). This method eliminates the power loss and board area associated with a dedicated sense resistor, improving efficiency and simplifying layout in the HIP6004BCVZ-based design.
How is the output voltage programmed on the HIP6004BCVZ?
The HIP6004BCVZ output voltage is programmed using a 5-bit TTL-compatible digital-to-analog converter (DAC) accessed via VID0–VID4 pins (pins 4–8). These pins accept logic-high or logic-low signals to select one of 32 discrete DACOUT voltages ranging from 1.30V to 3.50V in 0.05V steps (1.3–2.05V) and 0.1V steps (2.1–3.5V). The DACOUT voltage directly sets the regulation reference, PGOOD window, and OVP threshold-no external resistors or DAC ICs are needed.
What is the function of the PGOOD pin on the HIP6004BCVZ?
The PGOOD pin (pin 12) on the HIP6004BCVZ is an open-drain output that signals when the regulated output voltage is within ±10% of the DACOUT reference. It pulls low during undervoltage or overvoltage faults and goes high-impedance (allowing external pull-up) when valid. Notably, the '11111' VID combination forces PGOOD high even though the regulator is disabled-enabling safe AND-ing of PGOOD signals in dual-CPU systems without false resets.
Can the HIP6004BCVZ operate with a +5V input supply instead of +12V?
Yes, the HIP6004BCVZ supports operation from either +5V or +12V input, as explicitly stated in the datasheet features and absolute maximum ratings. However, the recommended operating condition specifies VCC = +12V ±10%, and the gate drivers are optimized for 12V bias-using +5V may limit UGATE/LGATE drive strength and maximum achievable switching frequency. For +5V operation, verify gate drive margins and ensure sufficient bootstrap voltage generation for the high-side FET.
HIP6004BCVZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, Intel Pentium®, II, Pro
- Voltage - Input:
- 5V, 12V
- Number of Outputs:
- 1
- Voltage - Output:
- 1.3V ~ 3.5V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-TSSOP
HIP6004BCVZ FAQ
1.How can I place an order for HIP6004BCVZ through Aetrix?
Please submit a Request for Quotation (RFQ) for HIP6004BCVZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HIP6004BCVZ reliable?
The price and inventory of HIP6004BCVZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HIP6004BCVZ is usually 5 days.
3.What payment methods are accepted for HIP6004BCVZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HIP6004BCVZ transactions.
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4.How is shipping managed for HIP6004BCVZ?
HIP6004BCVZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HIP6004BCVZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HIP6004BCVZ?
For technical support, including HIP6004BCVZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HIP6004BCVZ requirements.
6.How does Aetrix verify that HIP6004BCVZ is sourced from the original manufacturer or authorized distributors?
All HIP6004BCVZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HIP6004BCVZ meets industry standards.
7.What is the process for return or replacement of HIP6004BCVZ?
All HIP6004BCVZ units undergo pre-shipment inspection (PSI). If there is an issue with HIP6004BCVZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HIP6004BCVZ part is unused and in its original packaging.
Return procedure for HIP6004BCVZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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