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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Analog Devices Inc. HMC4069LP4ETR

Name: HMC4069LP4ETR
Brand: Analog Devices Inc.
SKU: HMC4069LP4ETR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: HMC4069LP4ETR

Manufacturer:: Analog Devices Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 24-VFQFN Exposed Pad

Datasheet:: HMC4069LP4ETR.pdf

Description:: IC PLL FRACTIONAL-N VCO

Quantity:: RFQ Add To RFQ list

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Product details

Overview

HMC4069LP4ETR from Analog Devices is a 2.9 GHz integer-N synthesizer IC with integrated phase-frequency detector (PFD), 5-bit frequency counter, lock detect, and invert functionality. It operates with REF input from 10–1300 MHz and VCO input from 10–2900 MHz, supports programmable division ratios N = 2–32, delivers ultra-low SSB phase noise of –151 dBc/Hz @ 10 kHz offset (100 MHz REF), and is packaged in a 24-pin 4×4 mm QFN with exposed ground paddle for RF/thermal performance - used in low-noise PLLs for point-to-point radios and satellite comms.

For engineers reviewing the HMC4069LP4ETR datasheet, HMC4069LP4ETR pinout, HMC4069LP4ETR application, or HMC4069LP4ETR equivalent, this page provides verified technical context, real-world design meaning for key specs (e.g., PFD gain = 0.32 V/Rad, NU/ND output swing = 2 V_p-p, LD open-collector logic interface), and confirmed alternative options for synthesizer loop design requiring fast switching, wide loop bandwidth, and sub-150 dBc/Hz phase noise floor.

Technical Context

The HMC4069LP4ETR implements a high-speed digital phase-frequency detector comparing rising edges of differential REF and VCO inputs, generating pulsed NU (up) and ND (down) outputs to drive an external op-amp loop filter. Its 5-bit counter enables integer division with N = 2–32, while the INV pin allows hardware-level swapping of REF/VCO signal paths to correct layout mismatches without PCB rework.

Lock detection uses an open-collector LD output requiring a 1 kΩ pull-up to Vcc and RC filtering to convert narrow zero-crossing pulses into a stable logic-level voltage (LOW = unlocked, HIGH = locked). The device requires DC-coupled differential RF inputs (REF/NREF, VCO/NVCO) with external DC blocking capacitors and operates across –40°C to +85°C at Vcc = 4.75–5.25 V.

Key Specifications

Parameter	Value and Actual Design Meaning
REF Input Frequency	10–1300 MHz: supports wideband reference sources including crystal oscillators, TCXOs, and RF synthesizers; square wave input preferred for best phase noise at lower frequencies.
VCO Input Frequency	10–2900 MHz: enables direct synthesis up to X-band; requires external DC blocking on differential VCO/NVCO pins.
SSB Phase Noise	–151 dBc/Hz @ 10 kHz offset (100 MHz REF, +5 dBm): enables fast-locking, low-jitter PLLs with wide loop bandwidth and minimal spurious content.
PFD Gain	0.32 V/Rad: defines loop filter scaling factor; directly determines tuning voltage slope per phase error in closed-loop operation.
NU / ND Output Swing	2 V_p-p into high-Z load: compatible with standard op-amp integrators; outputs remain at ~5 V when inactive, pulse between 3–5 V when active.
Supply Current	295 mA @ Vcc = 5.0 V: dictates thermal management requirements; junction temperature rises ~9.5°C/W above ambient due to exposed paddle thermal path.
Lock Detect Output	Open-collector, 5 mA sink capability: requires external 1 kΩ pull-up and RC filter (e.g., 10 kΩ + 10 nF) to generate clean logic-level lock status for system monitoring.

Pinout & Package

Package: 24-pin, 4 × 4 mm leadless QFN with exposed ground paddle (RoHS-compliant, MSL1, matte Sn finish, marking "H4069" + 4-digit lot code). Paddle must be soldered to solid RF/DC ground plane using ≥8 thermal vias.

Pin/Terminal	Circuit Role	Design Meaning
1 (NU)	PFD Up Output	Pulsed high-Z output active when VCO frequency > REF frequency; must not be loaded below 2.5 V to prevent damage.
2 (ND)	PFD Down Output	Pulsed high-Z output active when VCO frequency < REF frequency; same voltage constraints as NU.
4 (Vcc)	Power Supply	+4.75 to +5.25 V supply; decoupling required near pin with 100 pF (RF) + 4.7 µF (bulk) capacitors.
7–11 (A0–A4)	Division Ratio Control	CMOS/TTL-compatible 5-bit parallel input defining N = 2–32 per truth table; LSB = A0.
14, 15 (VCO, NVCO)	Differential VCO Input	DC-coupled RF inputs requiring external series DC-blocking capacitors; matched 50 Ω trace routing critical.
19 (LD)	Lock Detect Output	Open-collector transistor output; requires 1 kΩ pull-up to Vcc and RC filter to generate stable logic HIGH/LOW for lock status.
20 (INV)	Invert Function Control	Logic HIGH swaps REF/VCO roles at PFD; enables correction of swapped loop filter op-amp inputs without hardware change.
21, 22 (REF, NREF)	Differential REF Input	DC-coupled reference inputs; same routing and blocking requirements as VCO pair.
23, 24 + Paddle	Ground Terminals	All are RF/DC ground connections; paddle must be soldered to internal/external ground plane with multiple vias for thermal and impedance control.

Key Features

Feature	Design Value
Ultra-low SSB phase noise floor	–151 dBc/Hz @ 10 kHz offset enables PLL designs with >100 kHz loop bandwidth and minimal close-in jitter.
Integrated lock detect with filtering guidance	Open-collector LD output includes explicit RC filter design rules (e.g., R > 100 Ω, C chosen for cutoff << REF frequency) for reliable system-level lock monitoring.
Hardware invert function (INV pin)	Swaps REF/VCO inputs at PFD level - eliminates need for PCB respin when loop filter op-amp inputs are misrouted.
Differential RF inputs with DC coupling	VCO/NVCO and REF/NREF pairs support direct connection to baluns or differential VCOs; external DC blocks mandatory to prevent bias disruption.
Exposed ground paddle thermal design	9.5 °C/W junction-to-paddle thermal resistance enables sustained 295 mA operation at +85°C ambient with proper PCB grounding.

Applications

Point-to-Point Microwave Radios	Satellite Communication Transceivers
Use Scenario: High-capacity backhaul links operating in 6–42 GHz bands requiring fast frequency agility and low EVM under dynamic channel conditions. IC Role / Device Role / Timing Role: Integer-N synthesizer core in PLL-based local oscillator subsystem, generating clean LO signals for up/down conversion with sub-150 dBc/Hz phase noise. Use Value: Enables <100 µs lock time and <0.5° RMS jitter over 10 kHz–10 MHz offset, meeting IEEE 802.16 and ETSI EN 302 217 spectral mask requirements.	Use Scenario: LEO/MEO satellite transponders needing radiation-tolerant, low-phase-noise LO generation for QPSK/8PSK modulation in harsh thermal environments. IC Role / Device Role / Timing Role: Reference-to-VCO phase alignment engine in redundant PLL architectures, leveraging LD output for autonomous lock health monitoring. Use Value: Delivers consistent –151 dBc/Hz phase noise across –40°C to +85°C, supporting BER <1e–6 at 100 Msps symbol rates without additional clean-up stages.
Military Radar Waveform Synthesis	Sonet/SDH Clock Recovery
Use Scenario: AESA radar systems requiring rapid frequency hopping across multi-GHz spans with deterministic phase continuity between hops. IC Role / Device Role / Timing Role: Fast-switching N-divider in hybrid PLL/direct-digital synthesizer (DDS) architectures, where INV pin simplifies calibration of I/Q path skew. Use Value: Achieves <50 µs settling with N = 2–32 reprogramming via parallel A0–A4, enabling PRF agility without loop filter redesign.	Use Scenario: OC-192/STM-64 line cards recovering 9.953 Gbps clock from degraded optical data streams with high jitter tolerance. IC Role / Device Role / Timing Role: Low-noise reference multiplier in clock and data recovery (CDR) PLLs, locking to 155.52 MHz or 622.08 MHz tributary clocks. Use Value: Provides <–150 dBc/Hz integrated jitter (12 kHz–20 MHz) for <0.3 UI_pp total jitter, satisfying Telcordia GR-253-CORE jitter transfer compliance.

Point-to-Point Microwave Radios

Satellite Communication Transceivers

Use Scenario: High-capacity backhaul links operating in 6–42 GHz bands requiring fast frequency agility and low EVM under dynamic channel conditions.

IC Role / Device Role / Timing Role: Integer-N synthesizer core in PLL-based local oscillator subsystem, generating clean LO signals for up/down conversion with sub-150 dBc/Hz phase noise.

Use Value: Enables <100 µs lock time and <0.5° RMS jitter over 10 kHz–10 MHz offset, meeting IEEE 802.16 and ETSI EN 302 217 spectral mask requirements.

Use Scenario: LEO/MEO satellite transponders needing radiation-tolerant, low-phase-noise LO generation for QPSK/8PSK modulation in harsh thermal environments.

IC Role / Device Role / Timing Role: Reference-to-VCO phase alignment engine in redundant PLL architectures, leveraging LD output for autonomous lock health monitoring.

Use Value: Delivers consistent –151 dBc/Hz phase noise across –40°C to +85°C, supporting BER <1e–6 at 100 Msps symbol rates without additional clean-up stages.

Military Radar Waveform Synthesis

Sonet/SDH Clock Recovery

Use Scenario: AESA radar systems requiring rapid frequency hopping across multi-GHz spans with deterministic phase continuity between hops.

IC Role / Device Role / Timing Role: Fast-switching N-divider in hybrid PLL/direct-digital synthesizer (DDS) architectures, where INV pin simplifies calibration of I/Q path skew.

Use Value: Achieves <50 µs settling with N = 2–32 reprogramming via parallel A0–A4, enabling PRF agility without loop filter redesign.

Use Scenario: OC-192/STM-64 line cards recovering 9.953 Gbps clock from degraded optical data streams with high jitter tolerance.

IC Role / Device Role / Timing Role: Low-noise reference multiplier in clock and data recovery (CDR) PLLs, locking to 155.52 MHz or 622.08 MHz tributary clocks.

Use Value: Provides <–150 dBc/Hz integrated jitter (12 kHz–20 MHz) for <0.3 UI_pp total jitter, satisfying Telcordia GR-253-CORE jitter transfer compliance.

Equivalent & Alternatives

The following parts are listed as comparable options for similar integer-N synthesizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
HMC4069LP4E	Same die, tape-and-reel packaging without ETR suffix; identical electrical specs and pinout.	No functional difference; HMC4069LP4ETR is the standard production orderable version with full traceability.	Select HMC4069LP4ETR for volume production requiring RoHS-compliant, MSL1-rated, fully tested units with lot traceability.
ADF4107BRUZ	Lower max VCO input (2.5 GHz vs. 2.9 GHz); no differential REF/VCO inputs; uses serial SPI interface instead of parallel A0–A4.	Better suited for cost-sensitive, space-constrained designs where serial control and integrated charge pump reduce BOM count.	Choose ADF4107BRUZ only if system already uses SPI-controlled PLLs and VCO range ≤2.5 GHz; not drop-in compatible due to interface and RF pin architecture differences.

Compared with HMC4069LP4ETR, the HMC4069LP4E offers identical performance but lacks ETR's enhanced traceability and packaging consistency for high-reliability programs, while the ADF4107BRUZ trades RF bandwidth and differential interface for integration and serial configurability - making HMC4069LP4ETR the optimal choice for wideband, low-phase-noise, parallel-programmed synthesizer designs demanding robust RF layout control.

Availability

HMC4069LP4ETR is available at Aetrix Electronics and suitable for point-to-point radios, satellite communication transceivers, and military radar waveform synthesis requiring stable component supply, full MSL1 handling compliance, and guaranteed long-term availability through Analog Devices' qualified product lifecycle program.

Supply support for HMC4069LP4ETR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and RF ICs, serving precision instrumentation, communications, and defense markets since 1965.

The HMC4069LP4ETR belongs to Analog Devices' Hittite Microwave RFIC product line, designed specifically for high-frequency, low-phase-noise frequency synthesis in microwave and millimeter-wave infrastructure where signal purity and layout flexibility are critical.

FAQ

What is the maximum VCO input frequency supported by the HMC4069LP4ETR?

The HMC4069LP4ETR supports VCO input frequencies from 10 MHz to 2900 MHz. This 2.9 GHz upper limit enables direct synthesis in L-, S-, and C-bands without prescaling, and is validated across the full operating temperature range (–40°C to +85°C) with input power between –10 dBm and +5 dBm. Operation beyond 2900 MHz is not characterized and may degrade phase noise or lock reliability.

Does the HMC4069LP4ETR require external DC blocking capacitors on its RF inputs?

Yes, the HMC4069LP4ETR requires external DC blocking capacitors on both differential RF input pairs: REF/NREF (pins 21/22) and VCO/NVCO (pins 14/15). These inputs are DC-coupled internally, so series capacitors (e.g., 100 pF, 0402, 50 V) must be placed immediately before the package to prevent bias disruption from external sources and ensure proper common-mode rejection.

How is lock detection implemented on the HMC4069LP4ETR, and what external components are needed?

The HMC4069LP4ETR implements lock detection via an open-collector LD pin (pin 19) that sinks current when unlocked. A 1 kΩ pull-up resistor to Vcc and an RC filter (e.g., 10 kΩ + 10 nF) are mandatory to convert narrow zero-crossing pulses into a stable logic-level output: average HIGH = locked, LOW = unlocked. Without filtering, the raw LD output contains high-frequency content unsuitable for direct microcontroller interfacing.

Can the HMC4069LP4ETR be used with single-ended REF or VCO inputs?

No - the HMC4069LP4ETR requires true differential inputs on both REF/NREF and VCO/NVCO pins. Single-ended drive degrades common-mode rejection, increases even-order distortion, and compromises phase noise performance. If only single-ended sources are available, a balun (e.g., Marki BAL-0006SMG) must be used to convert to differential mode prior to connection.

What is the purpose of the INV pin on the HMC4069LP4ETR, and how does it affect PFD operation?

Pin 20 (INV) swaps the internal assignment of REF and VCO inputs to the phase-frequency detector. When logic HIGH, the PFD compares rising edges as if REF were connected to the VCO input pins and vice versa - effectively reversing NU and ND output polarity. This allows correction of layout errors where REF and VCO traces were accidentally interchanged, eliminating the need for PCB rework.

HMC4069LP4ETR Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: Clock

Output:: Clock

Number of Circuits:: 1

Ratio - Input:Output:: 1:1

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 2.9GHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 4.75V ~ 5.25V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

HMC4069LP4ETR FAQ

1.How can I place an order for HMC4069LP4ETR through Aetrix?

Please submit a Request for Quotation (RFQ) for HMC4069LP4ETR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for HMC4069LP4ETR reliable?

The price and inventory of HMC4069LP4ETR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HMC4069LP4ETR is usually 5 days.

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HMC4069LP4ETR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your HMC4069LP4ETR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for HMC4069LP4ETR?

For technical support, including HMC4069LP4ETR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HMC4069LP4ETR requirements.

6.How does Aetrix verify that HMC4069LP4ETR is sourced from the original manufacturer or authorized distributors?

All HMC4069LP4ETR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HMC4069LP4ETR meets industry standards.

7.What is the process for return or replacement of HMC4069LP4ETR?

All HMC4069LP4ETR units undergo pre-shipment inspection (PSI). If there is an issue with HMC4069LP4ETR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The HMC4069LP4ETR part is unused and in its original packaging.

Return procedure for HMC4069LP4ETR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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