Analog Devices Inc. HMC536LP2
- Part No.:
- HMC536LP2
- Manufacturer:
- Analog Devices Inc.
- Category:
- RF Switches
- Package:
- 6-TDFN Exposed Pad
- Datasheet:
-
HMC536LP2.pdf
- Description:
- IC RF SWITCH SPDT 6GHZ 6DFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,037
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
HMC536LP2 from Analog Devices (formerly Hittite Microwave) is a GaAs MMIC SPDT T/R switch operating from DC to 6 GHz, featuring 0.6 dB typical insertion loss at DC–3 GHz, +33 dBm input P0.1dB at +5 V control, and 27 dB isolation at DC–4 GHz. It serves as a high-linearity transmit/receive path selector in cellular infrastructure RF front-ends.
For engineers reviewing the HMC536LP2 datasheet, HMC536LP2 pinout, HMC536LP2 application, or HMC536LP2 equivalent, key selection criteria include its positive-control logic (0/+3V or 0/+5V), 2×2 mm DFN LP2 package with exposed ground paddle, +54 dBm input IP3 at 0.5–1.0 GHz, and suitability for space-constrained, high-frequency T/R switching in WiMAX and CMTS systems.
Technical Context
The HMC536LP2 integrates GaAs pHEMT transistor arrays with on-chip bias control circuitry enabling single-supply positive-voltage operation (0/+3V or 0/+5V), eliminating need for negative rails. Its SPDT T/R architecture routes RF between RFC (common port) and either RF1 or RF2 based on complementary A/B logic states.
DC-coupled 50 Ω ports require external blocking capacitors; the exposed ground paddle and pins 2/4/6 must be soldered directly to PCB RF ground for optimal isolation (>27 dB) and thermal performance (θJA = 75 °C/W). Switching speed is 33 ns (tRISE/tFALL) and 70 ns (tON/tOFF) across full 0–6 GHz band.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Frequency Range | DC to 6 GHz - supports broadband T/R switching without band-switching hardware |
| Insertion Loss | 0.6 dB typ. (DC–3 GHz) - minimizes signal attenuation in critical receive paths |
| Isolation | 27 dB min. (DC–4 GHz) - prevents transmit leakage into receive chain during T/R transition |
| Input P0.1dB | +33 dBm @ +5 V - enables direct interface with high-power PA output stages |
| Input IP3 | +54 dBm @ 0.5–1.0 GHz - ensures low intermodulation distortion in multi-carrier base stations |
| Switching Speed | 33 ns tRISE/tFALL |
| Control Logic | Positive voltage: 0 V / +3 V or +5 V - simplifies interface with FPGA/GPIO without level shifters |
Pinout & Package
Package: 2×2 mm leadless DFN LP2 with exposed ground paddle (MSL1, Sn/Pb finish); requires full-solder connection of paddle and pins 2/4/6 to PCB RF ground plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A) | Control Input A | Logic input defining RF path state per truth table; accepts 0 V or +3/+5 V |
| 3 (B) | Control Input B | Complementary logic input; A/B pair selects RFC→RF1 or RFC→RF2 path |
| 2, 4, 6 (RFC, RF1, RF2) | RF Ports | DC-coupled 50 Ω RF terminals; require external DC blocking caps per lowest operating frequency |
| 5 (N/C) | No-Connect Terminal | Must be connected to RF ground to maximize isolation between RF1 and RF2 |
Key Features
| Feature | Design Value |
|---|---|
| Positive Control Interface | Operates with 0/+3 V or 0/+5 V logic - eliminates need for negative bias supplies or level translators |
| High Linearity | +54 dBm input IP3 at sub-1 GHz - preserves signal integrity in multi-tone LTE/WiMAX signals |
| Thermal Robustness | 0.86 W continuous dissipation at 85 °C with 75 °C/W thermal resistance - supports high-duty-cycle TDD operation |
| Miniaturized RF Layout | 4 mm² footprint with integrated ground paddle - reduces parasitic inductance and enables compact front-end modules |
Applications
| Cellular Base Station Transceivers | WiMAX/WiBro Subscriber Units |
|---|---|
Use Scenario: Full-duplex TDD transceiver in macrocell BTS using shared antenna between Tx and Rx chains. IC Role / Device Role / Timing Role: SPDT T/R switch routing PA output to antenna and LNA input from antenna under precise timing control. Use Value: 0.6 dB insertion loss preserves Rx sensitivity; +33 dBm P0.1dB handles PA output without compression. | Use Scenario: Outdoor CPE unit operating in 2.3–2.7 GHz WiMAX band with time-division duplexing. IC Role / Device Role / Timing Role: High-isolation RF path selector enabling single-antenna operation with minimal Tx-to-Rx leakage. Use Value: 27 dB isolation at 2.5 GHz prevents desensitization of LNA during high-power transmission bursts. |
| CATV/CMTS Upstream Path | RF Test Instrumentation |
Use Scenario: Upstream channel switching in cable modem termination systems supporting DOCSIS 3.1 upstream bonding. IC Role / Device Role / Timing Role: Low-loss RF path selector between multiple upstream modulators and common RF output. Use Value: DC–6 GHz bandwidth accommodates extended upstream spectrum up to 1.2 GHz with flat insertion loss. | Use Scenario: Signal routing matrix in automated RF test equipment requiring fast, repeatable path reconfiguration. IC Role / Device Role / Timing Role: High-speed, low-distortion RF switch enabling multi-port VNA calibration and stimulus routing. Use Value: 33 ns switching speed allows sub-100 ns path changes; +54 dBm IP3 maintains measurement accuracy under high-power test tones. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar T/R switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HMC349ALP3E | Wider bandwidth (DC–13 GHz), higher insertion loss (0.9 dB typ.), +5 V only control | Better suited for millimeter-wave test instrumentation above 6 GHz | Select when >6 GHz coverage is required and 0.3 dB higher loss is acceptable |
| Qorvo QM11036 | Same 2×2 mm DFN, +33 dBm P0.1dB, but requires dual-polarity control (−2.5 V / +2.5 V) | Designed for battery-powered portable radios where low-voltage logic is prioritized | Select only if system already provides negative rail; not drop-in compatible with HMC536LP2's positive-only control |
Compared with HMC349ALP3E and QM11036, the HMC536LP2 uniquely balances DC–6 GHz coverage, +54 dBm IP3, and single-supply positive control in a 4 mm² footprint-making it optimal for cost-sensitive, space-constrained infrastructure T/R designs without negative bias capability.
Availability
HMC536LP2 is available at Aetrix Electronics and suitable for cellular infrastructure, WiMAX subscriber units, and CATV/CMTS systems requiring stable component supply, RoHS-compliant sourcing, and long-term lifecycle support.
Supply support for HMC536LP2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global semiconductor leader specializing in high-performance analog, mixed-signal, and RF technologies for communications, industrial, and automotive markets.
The HMC536LP2 belongs to Analog Devices' legacy Hittite Microwave GaAs MMIC switch portfolio, engineered specifically for high-linearity, wideband T/R switching in wireless infrastructure and test equipment.
FAQ
What is the recommended DC blocking capacitor value for HMC536LP2 RF ports?
Capacitor value depends on lowest operating frequency: use ≥100 pF for 500 MHz minimum, ≥47 pF for 1 GHz minimum, and ≥10 pF for 3 GHz minimum. The evaluation board uses 100 pF 0402 capacitors. All RFC, RF1, and RF2 ports are DC-coupled and require external blocking caps; improper selection causes low-frequency roll-off or impedance mismatch in the HMC536LP2 signal path.
Does HMC536LP2 support both +3 V and +5 V control simultaneously?
No, HMC536LP2 supports either +3 V or +5 V control voltage-not both simultaneously. The control inputs A and B accept 0 V (low) and +3 V or +5 V (high) with ±0.2 V tolerance. Using +3 V yields +29 dBm P0.1dB; +5 V yields +33 dBm. Mixing voltages invalidates bias conditions and may degrade HMC536LP2 reliability or linearity.
Is the exposed ground paddle on HMC536LP2 electrically connected to internal die ground?
Yes, the exposed metal paddle on the bottom of the HMC536LP2 package is internally connected to RF/DC ground and must be soldered fully to the PCB ground plane. Thermal resistance (75 °C/W) and isolation (>27 dB) depend on this connection. Leaving the paddle unconnected degrades HMC536LP2 thermal performance and increases RF leakage between RF1 and RF2 ports.
What is the absolute maximum RF input power the HMC536LP2 can handle continuously?
The HMC536LP2 absolute maximum continuous RF input power is defined by its hot-switch power level: +29 dBm at +3 V control and +33 dBm at +5 V control. Exceeding these levels risks permanent damage. Derating applies above 85 °C ambient: dissipation must be reduced by 13.3 mW/°C. These limits apply regardless of duty cycle and are validated for HMC536LP2 operation across DC–6 GHz.
Can HMC536LP2 be used in systems requiring ESD protection beyond Class 1A?
No, HMC536LP2 has Class 1A HBM ESD rating (≤250 V), which is typical for GaAs MMICs. It is not rated for higher ESD classes. System-level ESD protection (e.g., external TVS diodes at RF ports) is required in environments exceeding IEC 61000-4-2 Level 2. Relying solely on HMC536LP2's intrinsic ESD robustness is insufficient for industrial or outdoor deployments where HMC536LP2 may be exposed to handling or field surges.
HMC536LP2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 6-TDFN Exposed Pad
- Packaging:
- Strip
- Product Status:
- Active
- RF Type:
- Cellular
- Topology:
- -
- Circuit:
- SPDT
- Frequency Range:
- 0Hz ~ 6GHz
- Isolation:
- 29dB
- Insertion Loss:
- 1dB
- Test Frequency:
- 6GHz
- P1dB:
- 33dBm
- IIP3:
- 52dBm
- Features:
- -
- Impedance:
- 50Ohm
- Voltage - Supply:
- 5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-DFN (2x2)
HMC536LP2 FAQ
1.How can I place an order for HMC536LP2 through Aetrix?
Please submit a Request for Quotation (RFQ) for HMC536LP2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HMC536LP2 reliable?
The price and inventory of HMC536LP2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HMC536LP2 is usually 5 days.
3.What payment methods are accepted for HMC536LP2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HMC536LP2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HMC536LP2?
HMC536LP2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HMC536LP2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HMC536LP2?
For technical support, including HMC536LP2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HMC536LP2 requirements.
6.How does Aetrix verify that HMC536LP2 is sourced from the original manufacturer or authorized distributors?
All HMC536LP2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HMC536LP2 meets industry standards.
7.What is the process for return or replacement of HMC536LP2?
All HMC536LP2 units undergo pre-shipment inspection (PSI). If there is an issue with HMC536LP2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HMC536LP2 part is unused and in its original packaging.
Return procedure for HMC536LP2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
HMC536LP2 Tags

-
BGS13SN8E6327XTSA1
Infineon Technologies

-
BGS12WN6E6327XTSA1
Infineon Technologies

-
BGS12P2L6E6327XTSA1
Infineon Technologies

-
BGS12PN10E6327XTSA1
Infineon Technologies

-
NJG1801K75-TE1
Nisshinbo Micro Devices Inc.

-
BGS14PN10E6327XTSA1
Infineon Technologies

-
SKY13348-374LF
Skyworks Solutions Inc.

-
4259-63
pSemi

-
PE42421SCAA-Z
pSemi

-
AS179-92LF
Skyworks Solutions Inc.

-
SKY13351-378LF
Skyworks Solutions Inc.

-
AS215-92LF
Skyworks Solutions Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

