Analog Devices Inc. HMC988LP3ETR

Overview

HMC988LP3ETR from Analog Devices (formerly Hittite Microwave) is an ultra-low-noise programmable clock divider and delay IC for high-precision timing distribution. It supports DC–4 GHz input/output, divides by 1/2/4/8/16/32, delivers ≤35 fsRMS integrated jitter at 100 MHz output, and provides 60-step 20 ps fine delay adjustment. It is deployed in basestation digital pre-distortion paths and high-performance ADC/DAC clocking systems.

For engineers reviewing the HMC988LP3ETR datasheet, HMC988LP3ETR pinout, HMC988LP3ETR application, or HMC988LP3ETR equivalent, this page delivers verified electrical specs, SPI-configurable coarse/fine delay architecture, LVPECL/LVDS/CML/CMOS input compatibility, on-chip regulator options, and real-world phase noise performance across 100 MHz–2 GHz outputs.

Technical Context

The HMC988LP3ETR implements a dual-stage delay architecture: coarse delay via SLIP-triggered cycle-skipping and fine delay using a 60-step 20 ps resolution delay line. Its synchronization logic supports soft/hard reset alignment across multiple devices on a shared SPI bus with up to eight addressable units (CHIP0–CHIP2).

It features dual supply operation-3.3 V direct or 5 V with optional internal regulator-and integrates on-die 50 Ω termination for differential inputs (100 Ω) and LVPECL outputs. Phase noise floor degrades ~15 dB when fine delay is enabled, confirming its design trade-off between flexibility and spectral purity.

Key Specifications

Pinout & Package

Package: 3 mm × 3 mm, 16-pin QFN with exposed paddle; RoHS-compliant, MSL1 rated, matte tin-plated copper alloy leads.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable clock divider and delay applications.

Compared with LTC6957-3 and HMC1034LP5E, the HMC988LP3ETR uniquely combines ultra-low-noise division, 60-step 20 ps fine delay, and SLIP-triggered coarse delay in a single 3×3 mm package-making it the only option for applications demanding both spectral purity and sub-cycle timing agility.

Availability

HMC988LP3ETR is available at Aetrix Electronics and suitable for basestation DPD, high-speed data converter clocking, backplane skew management, phase-coherent multi-channel synthesis, and automated test equipment requiring stable component supply and long-term lifecycle support.

Supply support for HMC988LP3ETR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Hittite Microwave in 2014 and maintains full product support, documentation, and manufacturing continuity for the HMC series.

The HMC988LP3ETR belongs to Analog Devices' high-frequency clock distribution product line, engineered specifically for ultra-low-jitter timing control in wireless infrastructure, defense radar, and precision instrumentation.

FAQ

What is the maximum input frequency supported by the HMC988LP3ETR?

The HMC988LP3ETR supports an input frequency range from DC to 4 GHz, as confirmed in Table 1 of the datasheet. This includes full functionality for divide-by-1 (bypass mode) up to 650 MHz, and full divider operation up to 4 GHz. The device maintains specified phase noise and jitter performance across this entire range when operated within recommended supply and termination conditions.

Does the HMC988LP3ETR support LVDS input signals?

Yes, the HMC988LP3ETR supports LVDS input signals, as explicitly stated in the "Flexible Input Interface" section: "LVPECL, LVDS, CML, CMOS Compatible." It accepts differential inputs on OSCP/OSCN pins with on-chip 50 Ω termination (100 Ω differential), and operates with AC or DC coupling. LVDS-compatible common-mode voltage range is specified as +1.6 V to +2.5 V.

How many HMC988LP3ETR devices can share a single SPI bus?

Up to eight HMC988LP3ETR devices can share a single SPI bus. This is enabled by three address pins (CHIP0, CHIP1, CHIP2), providing eight unique addresses (000–110), plus a dedicated broadcast address ("111"). Each device can be individually configured or updated simultaneously via broadcast mode, as detailed in the Theory of Operation section.

What is the purpose of the TRIG pin on the HMC988LP3ETR?

The TRIG pin on the HMC988LP3ETR serves as the external trigger input for synchronization (SYNC) and cycle-skip (SLIP) functions. It initiates hard-sync events to align output edges across multiple devices, or triggers SLIP operations to introduce coarse delay increments of one input cycle. Its use is limited to input frequencies ≤100 MHz due to internal timing constraints, as noted in the Synchronization Function description.

Can the HMC988LP3ETR operate from a 3.3 V supply without using the on-chip regulator?

Yes, the HMC988LP3ETR can operate directly from a 3.3 V supply by bypassing the on-chip regulator. In this mode, VDD5 is left unconnected or grounded, and the device draws power from the 3.3 V rail applied to VDD3_DECAP. Table 1 specifies VDD = +3.1 V to +3.5 V for bypass mode, and current consumption drops to 0.01 mA in standby-confirming full functionality without regulator activation.