Monolithic Power Systems Inc. HR1000AGS-P

Overview

HR1000AGS-P from Monolithic Power Systems is a resonant half-bridge controller IC designed for high-efficiency AC-DC power conversion in high-voltage topologies. It delivers complementary 50% duty-cycle gate drive signals with 350 ns fixed dead-time, supports up to 600 kHz switching frequency, integrates a bootstrap diode for high-side drive, and provides 1.5 A/2 A source/sink capability on both high-side (HG) and low-side (LG) drivers. It is used in LCD TV and telecom SMPS designs requiring zero-voltage switching and light-load burst-mode operation.

For engineers reviewing the HR1000AGS-P datasheet, HR1000AGS-P pinout, HR1000AGS-P application, or HR1000AGS-P equivalent, key selection considerations include its 600 V high-side floating capability, dual-level over-current protection (frequency-shift + latched shutdown), programmable oscillator range (via Fset/CT), soft-start timing control (SS pin), and PFC disable interface (PFC pin) - all critical for resonant converter stability and safety compliance.

Technical Context

The HR1000AGS-P implements a fixed-frequency-to-variable-frequency transition architecture: startup begins at maximum programmed frequency (e.g., 600 kHz) and gradually slows under feedback control to regulate output voltage via frequency modulation. Its oscillator uses a CT capacitor charged/discharged by current sources scaled from the 2.0 V reference at the Fset pin, enabling precise min/max frequency setting through external R–C networks.

Protection logic is hierarchical: primary over-current triggers frequency shift (CS > 0.8 V), while sustained over-current latches shutdown (CS > 1.5 V); brown-out (BO < 1.25 V), thermal (TJ > 150 °C), and latch-input (LATCH > 1.85 V) events cause non-latched or latched disable. Burst-mode activation (Burst < 1.25 V) halts gate outputs while preserving Fset reference and SS state to minimize quiescent consumption.

Key Specifications

Pinout & Package

HR1000AGS-P is housed in a 16-pin SOIC package with creepage-optimized layout: Pin 13 is unconnected (NC) to isolate high-voltage nodes (BST/SW) from low-side circuitry (GND/VCC/LG). The package supports surface-mount assembly and meets RoHS requirements.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resonant half-bridge controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1000AGS-P offers unique analog integration - including on-chip bootstrap diode, dual-threshold OCP, and dedicated PFC disable - making it optimal for high-reliability, medium-volume AC-DC supplies where layout simplicity and analog robustness outweigh digital flexibility.

Availability

HR1000AGS-P is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom SMPS modules, desktop PC ATX units, and open-frame AC-DC adapters requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for HR1000AGS-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The HR1000A product line targets high-efficiency resonant power conversion in consumer, computing, and telecom applications - emphasizing ZVS reliability, integrated protection, and simplified gate-drive architecture for 600 V-class half-bridge systems.

FAQ

What is the purpose of the NC pin (Pin 13) in the HR1000AGS-P SOIC-16 package?

Pin 13 is an unconnected (NC) terminal intentionally placed between SW (Pin 14) and HG (Pin 15) to increase creepage and clearance distances on the PCB. It serves no electrical function but enables compliance with safety standards (e.g., IEC 60950, UL 62368) in high-voltage resonant converter layouts by isolating the 600 V floating node from adjacent low-side signals.

How does the HR1000AGS-P implement zero-voltage switching (ZVS) in resonant half-bridge topologies?

ZVS is achieved through three integrated features: (1) fixed 350 ns dead-time between complementary HG and LG outputs to ensure complete MOSFET turn-off before opposite-side turn-on; (2) frequency modulation that lowers switching frequency under load to align resonance with MOSFET voltage zero-crossings; and (3) high dV/dt immunity (50 V/ns) on SW/BST pins to maintain timing integrity during fast transient events.

Can the HR1000AGS-P operate without an external PFC stage?

Yes - the PFC pin is optional and can be left floating or tied to VCC if no front-end PFC controller is present. The IC functions fully as a standalone resonant half-bridge controller: BO pin still provides brown-out protection, CS pin handles over-current, and burst-mode remains active. PFC disable functionality only engages when the pin is actively driven low by an external controller.

What is the minimum recommended CT capacitor value for reliable operation at –40°C?

For guaranteed operation at –40°C, MPS recommends CT ≤ 330 pF. At low temperatures, the internal Fset current source weakens slightly; a smaller CT capacitor ensures sufficient charging/discharging current to sustain stable oscillation across the full frequency range (e.g., 100–600 kHz) without cycle skipping or jitter.

How does the TIMER pin provide controlled short-circuit protection?

The TIMER pin implements a capacitor-based timeout: each CS > 0.8 V event injects 130 µA into the external capacitor. When voltage reaches 3.5 V, switching stops and the capacitor discharges. If voltage falls below 0.3 V, soft-start restarts. This creates intermittent "hiccup" mode under sustained short-circuit - limiting average power dissipation and preventing thermal runaway without requiring external timers.

Is the 2.0 V reference at the Fset pin buffered and load-independent?

Yes - the Fset pin provides a precision 2.0 V ±4% reference with internal buffering. It can source up to 2 mA (per datasheet absolute max) while maintaining regulation; typical applications use ≤100 µA for frequency-setting resistors, ensuring negligible loading effect on reference accuracy or temperature drift.

What layout guidance applies to the BST–SW node for stable high-side drive?

The BST–SW node must use a low-ESR, low-ESL ceramic capacitor (typically 0.1–0.22 µF) placed within 2 mm of Pins 16 and 14. SW trace should be short, wide, and routed over solid ground plane; avoid vias or splits under the capacitor. This minimizes parasitic inductance to prevent bootstrap voltage droop and ensure consistent 1.5 A source capability during high-frequency switching.