Monolithic Power Systems Inc. HR1001AGS

Overview

HR1001AGS from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller with adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), and two-level over-current protection (OCP) with auto-recovery. It operates up to 600 kHz, delivers 50% duty cycle control, and integrates 600 V high-side gate driver with bootstrap diode. Used in high-efficiency AC/DC SMPS for LCD TVs and telecom power supplies.

For engineers reviewing the HR1001AGS datasheet, HR1001AGS pinout, HR1001AGS application, or HR1001AGS equivalent, this page provides verified technical context, SOIC-16 package mapping, ADTA timing behavior, CMP fault response, and real-world soft-start frequency shift characteristics - all critical for resonant converter stability and ZVS optimization.

Technical Context

The HR1001AGS implements a variable-frequency, 50% duty-cycle control architecture optimized for LLC resonant converters, using CT capacitor charging/discharging modulated by FSET reference current to set f_min (60 kHz) and f_max (600 kHz). Its oscillator features valley/peak thresholds at 0.9 V and 3.8 V, enabling precise frequency regulation via external R_FSET and C_CT.

ADTA logic senses dv/dt at SW through HBVS pin using a 5 pF capacitor, dynamically adjusting dead time between 235 ns (min) and 1 µs (max) to maintain zero-voltage switching across load and line variations. CMP monitors CS polarity transitions relative to ±50–131 mV thresholds to block gate drive during capacitive-mode conditions, preventing shoot-through under short-circuit or severe overload.

Key Specifications

Pinout & Package

HR1001AGS is housed in a SOIC-16 package with creepage-enhanced layout: Pin 13 (NC) serves as high-voltage spacer between SW (Pin 14) and HG (Pin 15); GND (Pin 10) separates signal and pulsed current return paths per layout best practice.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1001AGS uniquely combines adaptive dead-time, capacitive mode protection, and 600 kHz variable-frequency control in a single SOIC-16 package - enabling higher efficiency, smaller magnetics, and intrinsic fault resilience in modern LLC designs.

Availability

HR1001AGS is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom AC/DC SMPS, and open-frame server PSUs requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for HR1001AGS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan.

The HR1001AGS belongs to MPS's LLC Resonant Controller product line, engineered specifically for high-efficiency, high-power-density AC/DC conversion in consumer, computing, and communications infrastructure.

FAQ

What is the minimum recommended CT capacitor value for stable operation?

The datasheet specifies CT capacitance between 0.1 nF and 1 nF, with ≤330 pF recommended for optimal temperature stability. At 470 pF (typical evaluation condition), oscillator accuracy remains within ±2% across –40°C to +125°C junction temperature, avoiding frequency drift-induced regulation errors.

How does the HR1001AGS implement capacitive mode protection without external comparators?

HR1001AGS embeds dual internal comparators on the CS pin that reference ±50–131 mV thresholds. When LG turns off, CS is compared to VCSNR (–50 to –131 mV); when HG turns off, it compares to VCSPR (+50 to +131 mV). If polarity mismatch occurs, gate drive is blocked for 52 µs before re-evaluation - all handled in hardware with no external components.

Can the HR1001AGS operate without connecting the HBVS pin?

Yes - if HBVS is left unconnected or tied to GND, ADTA disables and dead time defaults to a fixed 350 ns. While functional, this eliminates ZVS assurance at light load and increases risk of hard switching; MPS strongly recommends using the 5 pF HBVS capacitor for full performance.

What is the purpose of the NC pin (Pin 13) in the SOIC-16 package?

Pin 13 is a no-connect spacer designed to increase creepage distance between high-voltage SW (Pin 14) and HG (Pin 15). It has no internal connection and must remain unconnected on PCB to meet reinforced isolation requirements per IEC 60950-1 and UL 62368-1 standards.

How does the two-level OCP function differ from standard current limiting?

Level 1 OCP (V_CS = 0.78 V) initiates frequency shift to limit power throughput without interrupting operation; Level 2 OCP (V_CS = 1.5 V) triggers immediate shutdown with TIMER-based auto-recovery. This staged response prevents nuisance tripping during transient overloads while guaranteeing safety under sustained faults.

Is burst-mode operation compatible with continuous conduction mode (CCM) PFC front-ends?

Yes - burst mode activates only on the LLC stage (via BURST pin voltage <1.23 V) and does not interfere with upstream CCM PFC controllers. The HR1001AGS maintains regulated VCC and BO monitoring during burst intervals, ensuring seamless re-synchronization when load increases.

What thermal derating applies above 25°C ambient?

With θ_JA = 80°C/W on a 4-layer JEDEC PCB, maximum continuous power dissipation drops linearly: PD_MAX = (150°C − T_A) / 80°C/W. At 70°C ambient, PD_MAX = 1.0 W; thermal shutdown engages at 150°C junction, recovering at 120°C - confirmed by characterization data on page 7.