Monolithic Power Systems Inc. HR1001AGS-P

Overview

HR1001AGS-P from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller IC with adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), and two-level over-current protection (OCP) with auto-recovery. It operates up to 600 kHz, delivers 50% duty cycle control, and integrates 600 V high-side and ground-referenced low-side gate drivers in SOIC-16. It targets high-efficiency AC/DC power supplies for LCD TVs and telecom SMPS.

For engineers reviewing the HR1001AGS-P datasheet, HR1001AGS-P pinout, HR1001AGS-P application, or HR1001AGS-P equivalent, key selection considerations include ADTA-enabled ZVS optimization across load range, programmable burst-mode threshold (1.23 V), dual OCP thresholds (0.78 V shift / 1.5 V latch), and HBVS-based dv/dt sensing for robust dead-time control under light-load and short-circuit conditions.

Technical Context

The HR1001AGS-P implements a variable-frequency, 50% duty-cycle control architecture optimized for LLC resonant converters. Its oscillator uses CT capacitor charging/discharging between 0.9 V (valley) and 3.8 V (peak) with FSET-set current, enabling precise min/max frequency programming via R_fmin and R_fmax.

ADTA logic monitors SW node dv/dt via HBVS pin using an external 5 pF capacitor, dynamically adjusting dead time between 235 ns (min) and 1 µs (max) to maintain zero-voltage switching. CMP detects polarity reversal at CS during HG/LG turn-off events and enforces blanking before gate re-enablement to prevent destructive capacitive-mode conduction.

Key Specifications

Pinout & Package

HR1001AGS-P is housed in a standard SOIC-16 package with creepage-enhancing NC pin (Pin 13) and integrated bootstrap diode for high-side drive. The layout separates HV (BST, SW, HBVS) and signal (SS, CT, CS) domains to support safe 600 V half-bridge operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1001AGS-P uniquely combines ADTA, CMP, and two-level OCP in a single SOIC-16 package-enabling higher efficiency at light load, faster short-circuit response, and reduced external component count for high-reliability LLC power supplies.

Availability

HR1001AGS-P is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom rectifiers, and desktop PC SMPS requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for HR1001AGS-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan.

The HR1001A product line delivers enhanced LLC resonant controller solutions targeting high-efficiency, high-reliability AC/DC conversion in consumer, computing, and communications infrastructure.

FAQ

What is the purpose of the HBVS pin and how is it used?

The HBVS pin senses dv/dt at the half-bridge switching node (SW) via an external capacitor (typically 5 pF) to enable adaptive dead-time adjustment. When SW transitions, current through CHBVS pulls HBVS low; the controller measures this slope to dynamically set dead time between HG and LG outputs-ensuring zero-voltage switching across load and line conditions without manual tuning.

How does the two-level OCP function differ from standard over-current protection?

HR1001AGS-P implements two distinct OCP responses: at 0.78 V on CS, it shifts frequency upward to limit power (non-latching); at 1.5 V, it immediately halts switching and initiates TIMER-based auto-recovery. This staged approach prevents nuisance tripping during transients while guaranteeing shutdown during sustained faults-improving system robustness without external circuitry.

Can HR1001AGS-P operate without connecting the HBVS pin?

Yes-leaving HBVS unconnected defaults the controller to fixed 350 ns dead time. However, this eliminates adaptive dead-time adjustment and ZVS optimization at light load, increasing switching losses and EMI. For full performance, the HBVS-to-SW 5 pF capacitor and optional Schottky clamp (BAT54 to GND) are required per the datasheet.

What is the role of the TIMER pin during capacitive mode protection?

The TIMER pin is not directly involved in capacitive mode protection (CMP). CMP operates independently via CS polarity comparison and internal 52 µs timer; TIMER exclusively manages OCP duration and auto-recovery timing. During CMP events, SS is discharged after a 1 µs blanking delay-but TIMER remains unaffected unless CS also exceeds OCP thresholds.

How is burst-mode threshold adjusted, and what impact does it have on light-load efficiency?

Burst-mode threshold is fixed at 1.23 V on the BURST pin; efficiency is tuned by scaling the optocoupler feedback network to drive BURST below this level at target light-load current. When active, burst mode reduces quiescent current to 1.42 mA and gates off both drivers-cutting standby power to <0.3 W in compliant AC/DC adapters without sacrificing regulation accuracy.

Is the NC pin (Pin 13) required to be left floating, or can it be grounded?

Pin 13 (NC) must remain unconnected-no internal bond wire exists. Grounding it violates creepage requirements and risks compromising isolation between BST/SW and adjacent pins. The NC pin serves solely as a physical spacer to meet safety standards (e.g., UL 62368-1); any connection voids certification compliance and may cause field failures.