Monolithic Power Systems Inc. HR1001AGS-Z

Overview

HR1001AGS-Z from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller IC with adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), and two-level over-current protection (OCP) with auto-recovery. It operates up to 600 kHz, delivers 50% duty cycle control, and integrates 600 V high-side gate drivers with bootstrap diode. Used in high-efficiency AC/DC power supplies for LCD TVs and telecom SMPS.

For engineers reviewing the HR1001AGS-Z datasheet, HR1001AGS-Z pinout, HR1001AGS-Z application, or HR1001AGS-Z equivalent, this page provides verified technical context, SOIC-16 package mapping, real-world ADTA timing behavior, CMP fault response logic, and validated alternative controllers for resonant converter design.

Technical Context

The HR1001AGS-Z implements a variable-frequency, 50% duty-cycle control architecture optimized for LLC resonant converters, using CT capacitor charging/discharging with FSET-referenced current programming to set f_min (60 kHz) and f_max (600 kHz). Its oscillator features non-linear soft-start with exponential frequency decay from startup peak to closed-loop regulation.

ADTA logic senses dv/dt at SW via HBVS pin using a 5 pF capacitor, dynamically adjusting dead time between 235 ns (minimum) and 1 µs (maximum) to maintain zero-voltage switching across load and line conditions. CMP monitors CS polarity transitions relative to ±85 mV thresholds and enforces 52 µs blanking before blocking gate drive during capacitive-mode detection.

Key Specifications

Pinout & Package

HR1001AGS-Z is housed in a SOIC-16 package with creepage-enhanced layout, including NC pin (Pin 13) for high-voltage isolation. Pin 9 (HBVS) and Pin 14 (SW) are rated for 600 V operation with 50 V/ns slew rate immunity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC resonant controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1001AGS-Z uniquely combines ADTA, CMP, and two-level OCP in a single SOIC-16 package-enabling robust, self-protecting LLC designs without external fault-handling circuitry or dead-time calibration.

Availability

HR1001AGS-Z is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom SMPS, and open-frame AC/DC adapters requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for HR1001AGS-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

HR1001AGS-Z belongs to MPS's LLC resonant controller product line, engineered specifically for high-efficiency, high-reliability AC/DC conversion in consumer, computing, and communications infrastructure.

FAQ

What is the purpose of the HBVS pin, and what capacitor value is recommended?

The HBVS pin senses dv/dt at the SW node to enable adaptive dead-time adjustment. A 5 pF capacitor connected between SW and HBVS is recommended for typical designs with L_m = 870 µH, V_in = 450 V, and f_max = 140 kHz. This value balances reliable dv/dt detection against HBVS overvoltage risk, and must be selected using Equation (10) based on MOSFET C_oss and peak magnetizing current.

How does the two-level OCP function differ from standard OCP in LLC controllers?

HR1001AGS-Z implements frequency-shift OCP at V_CS = 0.78 V (soft limiting) and latched shutdown at V_CS = 1.5 V (hard protection). The TIMER pin tracks cumulative OCP events: if voltage exceeds 3.5 V, the IC shuts down completely and only resumes after TIMER decays below 0.28 V-enabling controlled auto-recovery without external reset circuitry.

Can the HR1001AGS-Z operate without connecting the HBVS pin?

Yes-the IC defaults to fixed 350 ns dead time when HBVS is unconnected or grounded. However, adaptive dead-time adjustment is disabled, increasing risk of hard switching at light load and reducing efficiency by up to 1.8% in typical 24 V/100 W TV power supplies. A Schottky diode (e.g., BAT54) from HBVS to GND is strongly recommended to clamp negative excursions and stabilize ADTA timing.

What is the role of the BURST pin, and how is its threshold configured?

The BURST pin enables burst-mode operation when its voltage falls below 1.23 V (typical), reducing quiescent current to 1.42 mA. Threshold hysteresis is 30–100 mV, preventing oscillation near the transition point. To disable burst mode, connect BURST directly to FSET; to enable it, route optocoupler feedback through a resistor divider that scales secondary-side error voltage to the 1.23 V threshold.

How does the soft-start function interact with the SS and TIMER pins during startup?

At power-on, SS begins charging via external R_SS–C_SS, forcing high initial switching frequency. If an OCP event occurs, TIMER charges at 130 µA per event; if TIMER reaches 2 V, SS discharges fully to force maximum frequency. If TIMER exceeds 3.5 V, the IC latches off. SS is internally discharged during UVLO, BO undervoltage, LATCH activation, or thermal shutdown-ensuring guaranteed restart behavior.

Is the HR1001AGS-Z pin-compatible with the HR1001B variant?

No-HR1001AGS-Z implements OCP auto-recovery (HR1001A), whereas HR1001B uses latch-off OCP. Their functional differences affect TIMER pin behavior, OCP recovery sequence, and fault-handling logic. Although both use SOIC-16 and share identical pinout, substituting HR1001B for HR1001AGS-Z will disable auto-recovery and alter burst-mode timing due to different internal reference calibrations.

What thermal derating guidance applies to the SOIC-16 package at elevated ambient temperatures?

With θ_JA = 80 °C/W on a 4-layer JEDEC PCB, the maximum continuous power dissipation drops from 1.56 W at 25 °C to 0.94 W at 70 °C ambient. Junction temperature must remain ≤125 °C for rated operation; thermal shutdown activates at 150 °C. Layout best practices include copper pour under exposed pad (if present), thermal vias to inner ground planes, and separation from heat-generating components.