Monolithic Power Systems Inc. HR1001BGS

Overview

HR1001BGS from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller with adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), 50% duty cycle control, 600 kHz max switching frequency, and integrated 600V high-side gate driver. It operates from 13–15.5 V_CC, supports programmable burst mode, and delivers robust protection for AC/DC SMPS in TVs, servers, and telecom power supplies.

For engineers reviewing the HR1001BGS datasheet, HR1001BGS pinout, HR1001BGS application, or HR1001BGS equivalent, key selection criteria include ADTA-enabled ZVS optimization across load range, dual-level OCP with latched shutdown, HBVS-based dv/dt sensing for dead-time tuning, and SOIC-16 package compatibility with high-voltage layout requirements.

Technical Context

The HR1001BGS implements a variable-frequency, 50% duty-cycle control architecture optimized for LLC resonant converters. Its oscillator uses CT capacitor charging/discharging between 0.9 V and 3.8 V thresholds, with FSET setting current to define min/max frequency via R_fmin and R_fmax network.

ADTA logic monitors SW node dv/dt through HBVS pin using external CHBVS capacitor (typically 5 pF) to dynamically adjust dead time between 180 ns and 1 µs. CMP detects current polarity reversal at CS pin relative to ±50–131 mV thresholds and enforces 52 µs blanking before fault response.

Key Specifications

Pinout & Package

HR1001BGS is housed in a SOIC-16 package with creepage-enhanced layout, including NC pin (Pin 13) for high-voltage isolation and BST/SW/HBVS pins rated for 600 V operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1001BGS uniquely integrates ADTA and CMP in SOIC-16, enabling single-chip ZVS assurance and short-circuit robustness without external comparators or timing ICs-critical for high-reliability telecom and display power.

Availability

HR1001BGS is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom rectifiers, and server SMPS requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for HR1001BGS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with focus on energy-efficient DC/DC, AC/DC, LED drivers, and motor drivers.

The HR1001BGS belongs to MPS's LLC Resonant Controller product line, engineered specifically for high-efficiency, high-power-density resonant converters in consumer, computing, and communications infrastructure.

FAQ

What is the purpose of the HBVS pin and how is it used in circuit layout?

The HBVS pin senses dv/dt at the SW node via an external capacitor (typically 5 pF) to enable adaptive dead-time adjustment. It must be routed with minimal trace length and no vias between SW and HBVS, placed close to the IC, and isolated from noisy grounds. A Schottky diode (e.g., BAT54) from HBVS to GND is recommended to clamp negative excursions and stabilize ADTA timing.

How does the two-level OCP function differ from standard over-current protection?

Level one OCP (at 0.78 V on CS) increases switching frequency to limit delivered power without interrupting operation; level two (at 1.5 V) forces latched shutdown requiring V_CC recycle. This staged response avoids nuisance tripping during transient surges while ensuring fail-safe shutdown under sustained overload-reducing need for external fault latches.

Can HR1001BGS operate without connecting the CS pin?

Yes-CS can be tied to GND to disable current sensing, OCP, CMP, and frequency-shift functions. However, this removes all primary-side protection and soft-start control, limiting use to fixed-frequency evaluation or non-critical applications where secondary-side regulation and external fault management are fully implemented.

What determines the minimum achievable dead time with ADTA enabled?

The minimum dead time is fixed at 180 ns (typical) and enforced by internal logic to prevent shoot-through, even if HBVS detects extremely fast dv/dt transitions. This hard lower bound ensures gate drive overlap is physically impossible, maintaining functional safety regardless of external component tolerances or layout parasitics.

How is burst mode triggered and what impact does it have on output regulation?

Burst mode activates when the voltage on the BURST pin falls below 1.23 V (with 30 mV hysteresis), causing the IC to halt switching and reduce quiescent current to ~1.5 mA. Output regulation remains tight because the feedback loop continues monitoring via FSET, and restart occurs within microseconds once BURST rises above 1.26 V-minimizing output ripple at light load.

Is the SOIC-16 package of HR1001BGS lead-free and RoHS compliant?

Yes-HR1001BGS is lead-free, halogen-free, and fully compliant with the EU RoHS directive. MPS confirms green status on its official Quality Assurance page, and the device meets JEDEC J-STD-020 moisture sensitivity level MSL3 for standard surface-mount assembly processes.