Monolithic Power Systems Inc. HR1001BGS-P

Overview

HR1001BGS-P from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller with adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), and programmable variable-frequency control. It delivers 50% duty cycle gate drive for high-efficiency ZVS operation, supports up to 600 kHz switching, and integrates 600 V high-side and ground-referenced low-side gate drivers with ±0.87 A peak sink/source capability. It is used in high-density AC/DC power supplies for LCD TVs and telecom SMPS.

For engineers reviewing the HR1001BGS-P datasheet, HR1001BGS-P pinout, HR1001BGS-P application, or HR1001BGS-P equivalent, key selection considerations include ADTA-enabled dv/dt-sensed dead-time tuning, dual-level OCP with latched shutdown, burst-mode quiescent current reduction below 1.5 mA, SOIC-16 creepage-optimized layout, and HBVS-based capacitive mode detection timing at 52 µs.

Technical Context

The HR1001BGS-P implements a resonant half-bridge control architecture with a modulated oscillator that charges/discharges the CT capacitor between 0.9 V and 3.8 V thresholds to set frequency. Its ADTA logic monitors SW node dv/dt via HBVS and dynamically adjusts dead time between 180 ns and 1 µs-ensuring zero-voltage switching across load and line variations.

Capacitive mode protection activates when CS voltage crosses polarity thresholds (VCSPR = +85 mV, VCSNR = −85 mV) during HG/LG turn-off transitions, triggering a 52 µs blanking timer before initiating SS discharge. The controller also features two-level over-current response: frequency shift above 0.78 V (OCR) and latched shutdown above 1.5 V (OCP), with programmable TIMER delay duration.

Key Specifications

Pinout & Package

HR1001BGS-P is housed in a standard SOIC-16 package with creepage-enhancing NC pin (Pin 13) and integrated bootstrap diode. Pin assignments are validated per MPS HR1001B Rev. 1.1 datasheet (March 2018).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1001BGS-P uniquely delivers production-ready adaptive dead-time control and integrated capacitive mode protection-reducing design iteration cycles and eliminating external fault-detection components in high-reliability LLC systems.

Availability

HR1001BGS-P is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom rectifiers, and industrial open-frame SMPS requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for HR1001BGS-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The HR1001B product line targets high-efficiency resonant AC/DC conversion, specifically engineered to simplify LLC half-bridge design through integrated ADTA, CMP, and programmable burst-mode control.

FAQ

What is the purpose of the HBVS pin, and how is it connected?

The HBVS pin senses dv/dt at the SW node via an external 5 pF capacitor to enable adaptive dead-time adjustment and capacitive mode protection. It must be connected directly between SW and HBVS with minimal trace length; adding a Schottky diode (e.g., BAT54) from HBVS to GND clamps negative excursions and stabilizes ADTA timing.

How does the HR1001BGS-P implement two-level over-current protection?

It uses dual CS voltage thresholds: at 0.71–0.85 V (OCR), the controller increases switching frequency to limit power; if current persists and exceeds 1.41–1.59 V (OCP), it triggers latched shutdown. The TIMER pin sets the maximum allowable duration between OCR detection and OCP activation, configurable via external RC.

Can the HR1001BGS-P operate without connecting the HBVS pin?

Yes, but ADTA and CMP functions are disabled. The controller defaults to a fixed 350 ns dead time and loses capacitive mode detection capability. This configuration sacrifices ZVS robustness at light load and removes critical short-circuit protection-strongly discouraged for production designs.

What is the recommended CT capacitor value for optimal temperature stability?

MPS recommends CT ≤ 330 pF for best overall temperature performance. Typical values range from 100 pF to 470 pF; lower values improve frequency stability across –40°C to +125°C junction temperature but require tighter tolerance resistors on FSET for accurate min/max frequency setting.

How does the burst mode function reduce standby power consumption?

When the BURST pin voltage falls below 1.17–1.28 V, the controller disables gate drive outputs and reduces ICC to 1.2–1.5 mA while maintaining feedback monitoring. Switching resumes immediately when BURST rises above 1.26 V (30 mV hysteresis), eliminating soft-start delay and enabling rapid load-response.

Is the NC pin (Pin 13) required to be left unconnected in PCB layout?

Yes-Pin 13 is electrically unconnected and serves solely as a creepage spacer. It must remain unconnected on the PCB and should not be tied to GND, VCC, or any other net. Its presence increases clearance between BST/SW and adjacent pins to meet IEC 62368 reinforced insulation requirements.

What thermal derating applies to the SOIC-16 package at elevated ambient temperatures?

With θJA = 80°C/W on a 4-layer PCB, maximum continuous power dissipation drops linearly: at TA = 70°C, PD(MAX) = (150°C − 70°C)/80°C/W = 1.0 W; at TA = 100°C, PD(MAX) = 0.625 W. Derating is enforced by internal thermal shutdown at 150°C with 30°C hysteresis.