Monolithic Power Systems Inc. HR1001BGS-Z

Overview

HR1001BGS-Z from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller with adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), and 50% duty cycle variable-frequency control. It operates up to 600 kHz, features integrated 600 V high-side gate driver with bootstrap diode, and delivers programmable burst mode, two-level OCP, and non-linear soft start. It targets high-efficiency AC/DC power supplies in LCD TVs and telecom SMPS.

For engineers reviewing the HR1001BGS-Z datasheet, HR1001BGS-Z pinout, HR1001BGS-Z application, or HR1001BGS-Z equivalent, key selection criteria include ADTA-enabled ZVS optimization across load range, CMP response time (52 µs), dual-threshold OCP (0.78 V / 1.5 V), SOIC-16 creepage-compliant layout, and FSET-referenced frequency modulation for closed-loop voltage regulation.

Technical Context

The HR1001BGS-Z implements a current-mode-controlled variable-frequency oscillator with CT capacitor charging/discharging between 0.9 V and 3.8 V thresholds, enabling precise min/max frequency setting via external R_FSET network. Its ADTA logic senses SW node dv/dt through HBVS pin using a 5 pF capacitor to dynamically adjust dead time between 180 ns and 1 µs-ensuring zero-voltage switching while preventing shoot-through.

Capacitive mode protection activates when CS voltage crosses polarity thresholds (±50–131 mV) during HG/LG turn-off transitions, triggering a 52 µs timer before forced SS discharge. The controller integrates dual OCP: frequency-shift regulation at 0.78 V (typ.) and latched shutdown at 1.5 V (typ.), with programmable TIMER pin timing for fault duration control.

Key Specifications

Pinout & Package

HR1001BGS-Z is housed in a standard SOIC-16 package with creepage-enhancing NC pin (Pin 13) separating high-voltage (BST, SW, HG) and low-voltage (GND, VCC, CS) domains. Pin 10 serves as common ground return for both bias and low-side gate drive currents, requiring separate signal and pulsed-current PCB traces.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1001BGS-Z uniquely integrates ADTA and CMP in SOIC-16, eliminating external dead-time tuning components and capacitive-mode fail-safe circuitry-reducing design cycle time by ~3 weeks and component count by 7.

Availability

HR1001BGS-Z is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom rectifiers, and desktop PC SMPS requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for HR1001BGS-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with over 20 years of expertise in DC/DC, AC/DC, and motor driver solutions.

The HR1001B product line targets high-density, high-efficiency resonant converters for consumer and telecom power supplies-designed to replace discrete control + protection implementations with single-chip ZVS optimization.

FAQ

What is the purpose of the NC pin (Pin 13) in the HR1001BGS-Z SOIC-16 package?

Pin 13 is a no-connect spacer that electrically isolates the high-voltage BST/SW domain from low-voltage GND/VCC domains. It increases creepage distance to meet IEC 60950-1 reinforced insulation requirements without requiring custom PCB slotting or wider spacing-reducing certification effort and board area.

How does the HR1001BGS-Z implement adaptive dead-time adjustment without external timing components?

The HR1001BGS-Z uses internal logic to monitor dv/dt at the SW node via HBVS pin and a 5 pF capacitor. When SW transitions, current through CHBVS pulls HBVS voltage; the controller measures this to calculate optimal dead time between HG and LG edges-ranging from 180 ns to 1 µs-without resistors, capacitors, or microcontroller intervention.

Can the HR1001BGS-Z operate without connecting the HBVS pin?

Yes-the controller defaults to fixed 350 ns dead time if HBVS is left unconnected. However, this eliminates ADTA benefits: ZVS may be lost at light loads, increasing MOSFET switching loss and thermal stress. For designs targeting >90% efficiency above 10% load, HBVS connection with 5 pF capacitor is mandatory.

What is the functional difference between the two OCP thresholds on the CS pin?

The CS pin has two distinct OCP levels: 0.78 V triggers frequency-shift regulation (raising f_SW to limit power), while 1.5 V initiates latched shutdown. This two-stage response prevents nuisance tripping during transient overloads while ensuring robust protection during sustained faults-eliminating need for external latch circuitry.

How does the TIMER pin coordinate with capacitive mode protection?

When CMP detects capacitive conduction, the TIMER capacitor begins charging at 130 µA. If voltage reaches 3.5 V within 52 µs, the controller shuts down switching and discharges SS to force restart. This ensures CMP faults are resolved within one switching cycle-preventing cumulative energy buildup that could destroy MOSFETs during output short circuits.

Is the HR1001BGS-Z compatible with GaN HEMTs in the half-bridge?

Yes-the 30 ns rise/fall times, 0.87 A sink capability, and 600 V SW rating support direct drive of enhancement-mode GaN HEMTs. Layout must minimize SW node inductance (<1 nH) to prevent false dv/dt detection on HBVS; use Kelvin-source connections and tight gate loop routing.

What is the minimum recommended CT capacitor value for stable operation?

MPS recommends CT ≤ 330 pF for best temperature stability. At 470 pF (typical eval board value), frequency drift exceeds ±3% over -40°C to +125°C. Using 220 pF CT with 12 kΩ R_FSET yields 60 kHz min frequency with <1.5% drift-critical for telecom SMPS requiring tight output regulation across temperature.