Monolithic Power Systems Inc. HR1001CGS

Overview

HR1001CGS from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller with adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), and two-level over-current protection. It delivers 50% duty cycle, variable-frequency control up to 600 kHz, integrated 600V high-side gate driver with bootstrap diode, and operates from 13–15.5 V supply for LCD TV and telecom SMPS power supplies.

For engineers reviewing the HR1001CGS datasheet, HR1001CGS pinout, HR1001CGS application, or HR1001CGS equivalent, this IC enables robust ZVS operation under light-load and overload conditions, supports programmable burst mode for <1.5 mA quiescent current, and provides dV/dt-sensed dead-time tuning via HBVS pin to prevent shoot-through in high-efficiency resonant converters.

Technical Context

The HR1001CGS implements a dual-loop frequency-modulated control architecture: primary regulation via FSET-pin optocoupler feedback modulates oscillator frequency between programmable f_min and f_max, while secondary soft-start and burst-mode logic act on SS and BURST pins. Its ADTA circuit senses SW node dV/dt through HBVS to dynamically adjust dead time between 180 ns and 1 µs-ensuring zero-voltage switching across load and line variations.

Capacitive mode protection uses polarity-sensitive CS threshold detection (VCSPR = 50–131 mV, VCSNR = −131 to −50 mV) with 52 µs timer blanking to block HG/LG turn-on during unsafe resonant tank reversal. Two-level OCP combines frequency-shift response (V_CS-OCR = 0.71–0.85 V) and latched shutdown (V_CS-OCP = 1.41–1.59 V) with programmable TIMER delay.

Key Specifications

Pinout & Package

HR1001CGS is housed in a SOIC-16 package with creepage-enhancing NC pin (Pin 13) isolating SW (Pin 14) from adjacent low-voltage signals. The layout-optimized pinout separates power (BST, HG, SW, LG, VCC, GND) and control (CS, CT, FSET, BURST, SS, TIMER, BO, LATCH, HBVS) domains to minimize noise coupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1001CGS uniquely integrates ADTA, CMP, and programmable burst mode in a single SOIC-16 package-enabling higher efficiency, safer overload behavior, and lower no-load power without external components or firmware intervention.

Availability

HR1001CGS is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom rectifiers, and desktop PC SMPS requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for HR1001CGS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global distribution through authorized partners.

The HR1001CGS belongs to MPS's enhanced LLC controller product line, engineered specifically for high-efficiency, high-reliability resonant power conversion in consumer, computing, and communications infrastructure applications.

FAQ

What is the purpose of the HBVS pin and how is it used?

The HBVS pin senses dV/dt at the SW node via an external capacitor (typically 5 pF) to enable adaptive dead-time adjustment. When SW transitions, current through CHBVS pulls HBVS voltage down; the IC uses this signal to dynamically set dead time between HG and LG outputs-ensuring zero-voltage switching across load and line variations without manual tuning.

How does capacitive mode protection (CMP) prevent MOSFET damage?

CMP monitors CS pin polarity after HG or LG turn-off using dedicated thresholds (VCSPR = 50–131 mV, VCSNR = −131 to −50 mV). If resonant tank current reverses before next gate transition, CMP blanks the opposite gate drive for 52 µs and discharges SS-blocking hard-switching and preventing destructive capacitive conduction during short-circuit or overload faults.

Can HR1001CGS operate without connecting the HBVS pin?

Yes-when HBVS is left unconnected, the IC defaults to fixed 350 ns dead time. However, ADTA functionality is disabled, eliminating automatic ZVS optimization. Fixed dead time may cause hard switching at light load or with large magnetizing inductance, increasing MOSFET stress and reducing efficiency compared to dV/dt-sensed operation.

What determines the minimum and maximum switching frequencies?

f_min is set by R_fmin from FSET to GND (f_min = 1/(3 × CT × R_fmin)); f_max is set by R_fmin || R_fmax (f_max = 1/(3 × CT × (R_fmin || R_fmax))). CT is typically 470 pF. Optocoupler modulation of FSET current adjusts operating frequency between these bounds for closed-loop regulation.

How does the two-level over-current protection work?

Level 1 (OCR) triggers at V_CS-OCR = 0.71–0.85 V, causing frequency shift to limit power. If current remains above V_CS-OCP = 1.41–1.59 V after TIMER capacitor charges to VTIMER-SD (3.2–3.7 V), Level 2 engages latched shutdown. This staged response avoids false trips during surge tests while ensuring robust fault clearance.

Is the SOIC-16 package thermally adequate for 600 kHz operation?

Yes-the SOIC-16 package has Θ_JA = 80°C/W and Θ_JC = 35°C/W (per JEDEC JESD51-7, 4-layer PCB). At 1.56 W max dissipation and 125°C max junction temperature, ambient must stay below 25°C for full-power continuous operation. For higher ambient, derating or PCB copper pour is recommended per MPS AN-107 thermal guidelines.