Monolithic Power Systems Inc. HR1001CGS-P

Overview

HR1001CGS-P from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller IC featuring adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), two-level over-current protection (OCP), programmable burst mode, and 600 kHz max switching frequency. It drives high-side and low-side MOSFETs in isolated AC/DC power supplies, delivers 50% duty cycle control, integrates a 600V high-side gate driver with bootstrap diode, and operates across –40°C to +125°C junction temperature.

For engineers reviewing the HR1001CGS-P datasheet, HR1001CGS-P pinout, HR1001CGS-P application, or HR1001CGS-P equivalent, this controller supports robust design of high-efficiency resonant converters for TVs, telecom SMPS, and open-frame adapters - with focus on surge resilience, ZVS assurance, light-load efficiency, and capacitive-mode fault prevention.

Technical Context

The HR1001CGS-P implements a variable-frequency, 50% duty-cycle control architecture optimized for LLC topology, using CT-based oscillator programming with FSET-referenced current sources to set min/max frequencies (60–600 kHz). Its ADTA logic senses dV/dt at SW via HBVS to dynamically adjust dead time between HG and LG outputs - maintaining zero-voltage switching across load and line variations.

Capacitive mode protection operates by comparing CS voltage against polarity thresholds (VCSPR = 50–131 mV, VCSNR = –131 to –50 mV) after each gate turn-off, enforcing a 52 µs blanking window before action. Two-level OCP combines frequency-shift regulation (VCS-OCR = 0.71–0.85 V) and latched shutdown (VCS-OCP = 1.41–1.59 V), with programmable timer delay and auto-recovery disabled only upon latch activation.

Key Specifications

Pinout & Package

HR1001CGS-P is housed in a 16-pin SOIC package with creepage-enhancing NC pin (Pin 13), internal bootstrap diode, and high-voltage isolation between BST/SW and GND domains. Pin functions are validated per MPS HR1001C Rev.1.0 datasheet (Feb 2017).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1001CGS-P uniquely delivers adaptive dead-time control, capacitive mode protection, and programmable burst mode in a single SOIC-16 package - enabling higher reliability, lower EMI, and better light-load efficiency without external components or firmware.

Availability

HR1001CGS-P is available at Aetrix Electronics and suitable for LCD/PDP TV power supplies, telecom rectifiers, and open-frame AC/DC adapters requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for HR1001CGS-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global distribution through authorized partners.

The HR1001C product line targets high-efficiency, high-reliability resonant power conversion - specifically engineered for LLC half-bridge topologies in consumer, telecom, and industrial power supplies where ZVS assurance and fault robustness are critical.

FAQ

What is the purpose of the HBVS pin and how is it used in circuit design?

The HBVS pin senses dV/dt at the SW node via an external capacitor (typically 5 pF) to enable adaptive dead-time adjustment. When SW transitions, current through CHBVS pulls HBVS voltage down; the IC uses this signal to detect slope polarity and magnitude, then dynamically adjusts dead time between HG and LG to ensure zero-voltage switching. Proper CHBVS selection - constrained by Equation (8) to keep dV/dt current below 65 mA - is essential for reliable ADTA operation and MOSFET protection.

How does the two-level over-current protection (OCP) function differ from standard OCP implementations?

HR1001CGS-P's two-level OCP first responds to over-current with frequency shift (triggered at VCS-OCR = 0.78 V), increasing switching frequency to limit delivered power. If current persists, it escalates to latched shutdown at VCS-OCP = 1.5 V, disabling all gate outputs until VCC cycles below UVLO. This staged response prevents false triggering during surge events while ensuring definitive protection during sustained faults - unlike single-threshold OCP that may latch prematurely or fail to respond to marginal overloads.

Can the HR1001CGS-P operate without connecting the HBVS pin, and what is the impact?

Yes, HR1001CGS-P can operate with HBVS left unconnected, but ADTA is disabled and dead time defaults to a fixed 350 ns. This eliminates automatic ZVS optimization across load conditions, increasing risk of hard switching at light load or with large magnetizing inductance. While functional for basic LLC operation, omitting HBVS forfeits key efficiency and reliability benefits - especially in designs requiring consistent ZVS over wide line/load ranges or high-power-density requirements.

What is the role of the TIMER pin and how is its timing behavior configured?

The TIMER pin implements a programmable delay between over-current detection and latched shutdown. An internal 80–180 µA current source charges an external capacitor when CS exceeds VCS-OCR; shutdown occurs when TIMER voltage reaches VTIMER-SD = 3.5 V. A parallel resistor discharges the capacitor slowly, setting restart delay. This allows adjustable fault-hold duration (e.g., 10–100 ms) and controlled burst-mode recovery - critical for surviving transient surges without system interruption.

How does the burst mode operation reduce no-load power consumption?

Burst mode reduces no-load power by disabling gate drive and entering ultra-low-quiescent-current state (1.2–1.8 mA) when feedback voltage at BURST falls below 1.23 V. In this state, the IC stops switching, halts oscillator activity, and maintains only essential bias circuits. It resumes normal operation only when BURST rises above 1.23 V + hysteresis (30–100 mV), eliminating continuous switching losses and enabling total system no-load consumption below 150 mW - meeting stringent Energy Star and EU CoC Tier 2 requirements.

Is the HR1001CGS-P compatible with synchronous rectification controllers?

HR1001CGS-P is not a synchronous rectification controller and does not provide SR gate drive signals. However, it is fully compatible with external SR controllers (e.g., MP6908, NCP4306) via its well-regulated output and stable timing - the FSET pin's 2.0 V reference and clean CT waveform allow precise feedback loop integration. Designers commonly pair HR1001CGS-P with dedicated SR ICs in high-efficiency LLC designs to achieve >95% overall efficiency.

What thermal protection mechanisms are built into the HR1001CGS-P?

HR1001CGS-P includes a thermal shutdown circuit that activates at TJ = 150°C (±5°C) and recovers at TJ = 120°C (±5°C). During shutdown, gate drivers disable, oscillator halts, and quiescent current drops to ~350 µA. The IC remains latched off until junction temperature falls below recovery threshold - preventing thermal runaway and enabling safe cooldown. Thermal parameters are characterized per JEDEC JESD51-7 on 4-layer PCB, with ΘJA = 80°C/W in SOIC-16 package.