Monolithic Power Systems Inc. HR1001CGS-Z

Overview

HR1001CGS-Z from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller IC featuring adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), two-level over-current protection, programmable burst mode, and 600V high-side gate driver with integrated bootstrap diode. It operates up to 600kHz, delivers 50% duty cycle control, and targets high-efficiency AC/DC power supplies in LCD TVs, telecom SMPS, and open-frame adapters.

For engineers reviewing the HR1001CGS-Z datasheet, HR1001CGS-Z pinout, HR1001CGS-Z application, or HR1001CGS-Z equivalent, key selection considerations include ADTA-enabled ZVS optimization across load range, CMP-triggered fault handling under short-circuit conditions, programmable frequency shift during soft-start, and HBVS-sensed dV/dt timing for robust half-bridge gate sequencing.

Technical Context

The HR1001CGS-Z implements a variable-frequency, 50% duty-cycle resonant control architecture with dual-loop modulation: primary frequency control via FSET-pin current programming and secondary regulation through optocoupler feedback into FSET. Its ADTA logic uses HBVS-sensed dV/dt current (via external CHBVS capacitor) to dynamically adjust dead time between HG and LG outputs - maintaining zero-voltage switching across light-to-heavy loads.

Capacitive mode protection activates when CS voltage crosses polarity thresholds (VCSPR = +85mV, VCSNR = −85mV) after HG/LG turn-off, triggering a 52µs blanking delay before SS discharge; this prevents destructive shoot-through during abnormal tank resonance. Two-level OCP combines frequency-shift limiting (VCS > 0.78V) and latched shutdown (VCS > 1.5V with VSS < 1.73V), both programmable via external RC networks on TIMER and CS pins.

Key Specifications

Pinout & Package

HR1001CGS-Z is housed in a standard SOIC-16 package with exposed pad (not thermally enhanced), compliant with JEDEC MS-012AC. Pin 13 (NC) serves as a high-voltage creepage spacer between SW (pin 14) and adjacent low-voltage signals, supporting reinforced isolation requirements in AC/DC applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1001CGS-Z uniquely integrates ADTA, CMP, and programmable burst mode in a single SOIC-16 package - delivering superior ZVS consistency, fault resilience, and light-load efficiency without requiring external compensation or protection ICs.

Availability

HR1001CGS-Z is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom SMPS, and open-frame AC/DC adapters requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for HR1001CGS-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global distribution through authorized partners.

The HR1001C product line targets high-efficiency resonant power conversion in consumer, telecom, and industrial AC/DC applications - emphasizing adaptive control, integrated protection, and simplified layout for robust, compact SMPS designs.

FAQ

What is the purpose of the HBVS pin and how is it used in ADTA?

The HBVS pin senses dV/dt at the SW node via an external capacitor (CHBVS, typically 5pF) to enable adaptive dead-time adjustment. When SW transitions, current through CHBVS pulls HBVS voltage down; the IC measures this slope to determine optimal dead time between HG and LG. If HBVS is left unconnected, dead time defaults to fixed 350ns, disabling ADTA functionality.

How does capacitive mode protection (CMP) prevent MOSFET failure during output short circuits?

CMP monitors CS polarity after HG or LG turn-off using thresholds VCSPR (+85mV) and VCSNR (−85mV). Upon detection, it enforces a 52µs blanking period before discharging SS - preventing immediate frequency ramp and allowing resonant tank energy to settle. This avoids hard-switching and shoot-through that would otherwise destroy MOSFETs under sustained short-circuit conditions.

Can HR1001CGS-Z operate without an external optocoupler?

Yes - the FSET pin accepts either optocoupler feedback for closed-loop regulation or a fixed resistor to GND for open-loop constant-frequency operation. For open-loop use, connect FSET to GND via Rfmin to set minimum frequency; omit optocoupler and tie BURST to FSET if burst mode is unnecessary. Regulation accuracy and load transient response will be reduced without feedback.

What is the role of the NC pin (Pin 13) in SOIC-16 layout?

Pin 13 is a no-connect spacer placed between SW (Pin 14) and VCC (Pin 12) to increase PCB creepage distance. It has no internal connection but is critical for meeting safety standards (e.g., UL/EN 62368-1) in 300VAC-input designs. Layout must maintain ≥4.5mm clearance from SW to all other pins, and NC should remain unconnected and unstubbed.

How is two-level over-current protection implemented and what triggers each level?

Level 1 OCP triggers when CS voltage exceeds 0.78V, causing immediate frequency shift upward to limit delivered power - useful for handling brief surges. Level 2 triggers when CS exceeds 1.5V *and* SS voltage drops below 1.73V, initiating latched shutdown requiring VCC recycle. The TIMER pin sets the duration between Level 1 detection and Level 2 activation, allowing controlled response to sustained overloads.

Does HR1001CGS-Z support synchronous rectification control?

No - HR1001CGS-Z is a primary-side LLC controller only and does not generate synchronous rectifier gate signals. It provides HG and LG outputs for the half-bridge primary MOSFETs and relies on external circuitry (e.g., TL431 + optocoupler or dedicated SR controller) for secondary-side regulation and rectification control.

What is the recommended CT capacitor value for optimal temperature stability?

MPS recommends CT ≤ 330pF for best overall temperature performance. Typical values range from 100pF to 470pF; lower values improve frequency stability over temperature but require tighter tolerance resistors on FSET. At CT = 470pF, fSW variation across −40°C to +125°C is ±3.5%, while at CT = 220pF, variation reduces to ±2.1%.