Monolithic Power Systems Inc. HR1001GS-Z

Overview

HR1001GS-Z from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller with adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), and programmable burst-mode operation. It delivers 50% duty cycle, variable-frequency control up to 600 kHz, integrated 600 V high-side gate driver with bootstrap diode, and two-level over-current protection for robust AC-DC power supplies in LCD TVs and telecom SMPS.

For engineers reviewing the HR1001GS-Z datasheet, HR1001GS-Z pinout, HR1001GS-Z application, or HR1001GS-Z equivalent, key selection criteria include ADTA-enabled ZVS assurance across load range, CMP-triggered shutdown under short-circuit, SOIC-16 thermal performance (θ_JA = 80 °C/W), and FSET-referenced frequency modulation via optocoupler feedback.

Technical Context

The HR1001GS-Z implements a dual-loop resonant control architecture: primary frequency-shift regulation via CT/FSET oscillator (min/max f_SW set by R_FMIN/R_FMAX), and secondary soft-start/burst-mode management via SS/TIMER/BURST pins. Its ADTA logic senses SW node dv/dt through HBVS to dynamically adjust dead time between 180 ns and 1 μs, preventing shoot-through while maintaining zero-voltage switching.

Capacitive mode protection operates independently per half-bridge transition: at HG turn-off, CS voltage is compared to +85 mV (VCSPR); at LG turn-off, to –85 mV (VCSNR). A mismatch triggers a 52 μs timer before blocking the complementary gate drive-ensuring MOSFET body-diode conduction does not lead to destructive cross-conduction.

Key Specifications

Pinout & Package

HR1001GS-Z is housed in a SOIC-16 package with exposed pad (not thermally enhanced), rated for θ_JA = 80 °C/W on 4-layer PCB per JESD51-7. Pin 13 is NC (high-voltage spacer) for creepage compliance; BST and SW pins support 600 V operation with 50 V/ns dv/dt immunity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1001GS-Z uniquely combines ADTA-driven ZVS assurance, CMP-triggered fault containment, and FSET-referenced optocoupler interface-enabling robust, high-efficiency LLC designs across variable line/load conditions without component recalibration.

Availability

HR1001GS-Z is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom rectifiers, and open-frame AC-DC adapters requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for HR1001GS-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The HR1001 belongs to MPS's resonant controller product line, engineered specifically for high-efficiency, high-reliability LLC half-bridge topologies in consumer and telecom power supplies.

FAQ

What is the minimum recommended HBVS capacitor value for reliable ADTA operation?

The minimum HBVS capacitor is determined by the resonant tank's peak magnetizing current and MOSFET output capacitance. For typical designs (L_m = 870 μH, V_IN = 450 V, f_SW-MAX = 140 kHz), 5 pF is specified. Using <3 pF risks missing dv/dt transitions below 180 V/μs, causing fixed 300 ns dead time and potential hard switching.

How does the two-level OCP function differ from standard current limiting?

Level one (0.78 V on CS) initiates frequency shift to reduce power without interrupting operation; level two (1.5 V) triggers latched shutdown requiring VCC recycle. This prevents nuisance tripping during transient surges while ensuring fail-safe response to sustained faults like output shorts or transformer saturation.

Can HR1001GS-Z operate without the HBVS pin connection?

Yes-HBVS can be left unconnected, resulting in fixed 300 ns dead time. However, this eliminates ADTA benefits: ZVS is lost at light load, increasing MOSFET switching loss and EMI. The datasheet explicitly states that ADTA functionality is disabled without HBVS, making it mandatory for full performance.

What is the purpose of the N.C. pin (Pin 13) in the SOIC-16 package?

Pin 13 is a non-connected high-voltage spacer. It isolates BST (600 V capable) and SW (600 V switching node) from adjacent low-voltage pins (GND, LG, VCC) to meet IPC-2221 creepage requirements for reinforced insulation in AC-DC applications-no routing or soldering is permitted.

How does burst-mode operation reduce no-load power consumption?

When BURST voltage falls below 1.25 V, HR1001GS-Z disables gate drivers and reduces quiescent current from 1.5 mA to 1.2 mA. Switching resumes only when feedback raises BURST above 1.35 V (100 mV hysteresis), eliminating standby losses without compromising regulation accuracy.

Is the FSET pin compatible with standard optocoupler feedback configurations?

Yes-FSET accepts current from an optocoupler phototransistor collector. A series resistor from FSET to VCC sets the minimum frequency; the phototransistor shunts this current to increase frequency for output regulation. This matches industry-standard TL431 + PC817 feedback topologies without additional level-shifting.