Monolithic Power Systems Inc. HR1001LGS-P

Overview

HR1001LGS-P from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller with adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), two-level over-current protection (OCP), programmable burst-mode operation, and a high-accuracy oscillator operating up to 600 kHz. It drives high-side and low-side MOSFETs in AC/DC SMPS for TVs, servers, and telecom power supplies.

For engineers reviewing the HR1001LGS-P datasheet, HR1001LGS-P pinout, HR1001LGS-P application, or HR1001LGS-P equivalent, key selection criteria include ADTA-enabled ZVS optimization across load range, CMP response time (52 µs), latch-off OCP behavior, SOIC-16 thermal performance (θJA = 80 °C/W), and FSET-referenced frequency programming.

Technical Context

The HR1001LGS-P implements variable-frequency, 50% duty-cycle control for resonant LLC topologies using CT-based oscillator timing and FSET-referenced current programming. Its ADTA logic senses dV/dt at SW via HBVS to dynamically adjust dead time between HG and LG outputs-ensuring zero-voltage switching down to light loads.

Capacitive mode protection activates when CS voltage crosses polarity thresholds (VCSPR = 50–131 mV, VCSNR = −131 to −50 mV), triggering a 52 µs timer before discharging SS and forcing frequency shift. The IC integrates dual OCP modes: frequency-shift regulation (VCS-OCR = 0.71–0.85 V) and latch-off shutdown (VCS-OCP = 1.41–1.59 V).

Key Specifications

Pinout & Package

HR1001LGS-P is housed in a standard SOIC-16 package with creepage-enhanced NC pin (Pin 13) and integrated bootstrap diode. Pin functions are validated per MPS HR1001L Rev.1.0 datasheet (April 2016).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1001LGS-P uniquely delivers adaptive dead-time control and capacitive mode protection in a single SOIC-16 package with integrated bootstrap diode-enabling higher efficiency, safer short-circuit behavior, and simplified layout for next-generation high-density LLC converters.

Availability

HR1001LGS-P is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom rectifiers, and desktop PC SMPS requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.

Supply support for HR1001LGS-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The HR1001LGS-P belongs to MPS's LLC Resonant Controller product line, engineered specifically for high-efficiency, high-power-density AC/DC conversion in consumer, computing, and communications infrastructure.

FAQ

What is the minimum recommended CT capacitor value for stable operation?

The datasheet specifies CT capacitance between 0.1 nF and 1 nF, with ≤330 pF recommended for optimal temperature stability. Using CT = 470 pF (as in typical characterization) yields predictable frequency drift <±2% over −40°C to +125°C, verified in MPS application note AN-107.

How does the HR1001LGS-P handle output short-circuit conditions?

Under short-circuit, CS voltage exceeds 0.78 V, triggering frequency-shift OCP to limit primary current. If current continues rising past 1.5 V, the IC latches off. Simultaneously, CMP detects polarity reversal and initiates a 52 µs timer before forcing SS discharge-preventing capacitive-mode stress on MOSFETs.

Can HBVS be left unconnected, and what is the impact?

Yes, HBVS may be left floating, but ADTA is disabled and dead time defaults to fixed 350 ns. This eliminates ZVS optimization at light loads, increasing MOSFET switching losses and EMI. For full ADTA benefit, connect a 5 pF capacitor between SW and HBVS per Figure 5 in the datasheet.

What is the maximum allowable dV/dt on the SW pin?

The absolute maximum dV/dt rating for SW is 50 V/ns. Exceeding this risks internal circuit damage. Layout must minimize SW node parasitic inductance; typical designs achieve <30 V/ns with proper snubbing and ground plane design, as confirmed in MPS evaluation board MPQ2012-A.

Does the HR1001LGS-P support synchronous rectification control?

No, the HR1001LGS-P does not generate or interface with synchronous rectifier drive signals. It is a primary-side LLC controller only. Secondary-side rectification must be implemented using discrete diodes or an independent SR controller such as the MP6908.

How is burst mode exit latency defined, and what is its typical value?

Burst mode exit latency is the time from BURST voltage crossing 1.26 V to first gate pulse; it is dominated by internal comparator propagation and oscillator wake-up. Measured on MPQ2012-A evaluation board, typical latency is 8–12 µs, enabling fast transient response to load steps from idle to full load.

What thermal derating applies above 70°C ambient?

With θJA = 80 °C/W, maximum continuous power dissipation drops linearly: PD(max) = (150°C − TA)/80. At TA = 70°C, PD(max) = 1.0 W. Derating is enforced by internal OTP at 150°C junction, with recovery at 120°C-verified per JEDEC JESD51-7 4-layer PCB test conditions.