Monolithic Power Systems Inc. HR1001LGS-Z

Overview

HR1001LGS-Z from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller featuring adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), two-level over-current protection (OCP), programmable burst mode, and a high-accuracy oscillator with dV/dt immunity. It delivers 50% duty cycle, variable-frequency control up to 600 kHz, and integrates 600 V high-side gate drivers with bootstrap diode. Used in high-efficiency AC/DC power supplies for LCD TVs and telecom SMPS.

For engineers reviewing the HR1001LGS-Z datasheet, HR1001LGS-Z pinout, HR1001LGS-Z application, or HR1001LGS-Z equivalent, key selection criteria include ADTA-enabled ZVS optimization across load range, CMP response time (52 µs), dual-threshold OCP (0.78 V / 1.5 V), SOIC-16 thermal performance (θJA = 80 °C/W), and HBVS dV/dt sensing interface for real-time dead-time tuning.

Technical Context

The HR1001LGS-Z implements a resonant control architecture where the CT/FSET oscillator sets min/max switching frequency (e.g., 60–200 kHz) via external R-C networks, while ADTA dynamically adjusts dead time between HG and LG outputs based on SW node dV/dt sensed through HBVS and CHBVS (5 pF typical). Its current-sense path (CS) enables both frequency-shift OCP and latch-off protection.

Capacitive mode protection operates by comparing CS voltage against polarity thresholds (VCSPR = 50–131 mV, VCSNR = –131 to –50 mV) after each gate transition, triggering a 52 µs timer before SS discharge - preventing destructive shoot-through during overload. The IC enters controlled burst mode when BURST pin voltage falls below 1.23 V, reducing quiescent current to 1.2 mA at light load.

Key Specifications

Pinout & Package

HR1001LGS-Z is housed in a standard SOIC-16 package with creepage-enhancing NC pin (Pin 13) and integrated bootstrap diode. Pin functions are validated per MPS HR1001L Rev.1.0 datasheet (April 2016).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, the HR1001LGS-Z uniquely combines ADTA, CMP, and dual-threshold OCP in a single SOIC-16 package-enabling robust ZVS across wide load ranges without external sensing components or protection ICs.

Availability

HR1001LGS-Z is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom SMPS, and desktop PC ATX PSUs requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for HR1001LGS-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan.

The HR1001L product line targets high-efficiency resonant AC/DC conversion, specifically engineered for LLC half-bridge topologies in consumer, computing, and telecom power supplies where ZVS reliability and light-load efficiency are critical.

FAQ

What is the purpose of the HBVS pin and how is it used?

The HBVS pin senses dV/dt at the SW node via an external capacitor (typically 5 pF) to enable Adaptive Dead-Time Adjustment. When SW transitions, current through CHBVS pulls HBVS voltage down; the IC uses this signal to dynamically adjust dead time between HG and LG outputs, ensuring zero-voltage switching across load conditions without manual tuning.

How does capacitive mode protection (CMP) operate during overload?

CMP monitors CS voltage polarity after each gate transition. If CS crosses VCSPR (50–131 mV) after HG turns off or VCSNR (–131 to –50 mV) after LG turns off, the IC starts a 52 µs timer. If polarity remains invalid after timeout, SS discharges to raise frequency and limit energy-preventing shoot-through before hard fault escalation.

Can HR1001LGS-Z be used without connecting the HBVS pin?

Yes, but ADTA is disabled. Without HBVS connection, dead time defaults to fixed 350 ns. While functional, this eliminates ZVS optimization at light loads and increases risk of hard switching or efficiency loss-especially with large magnetizing inductance or wide input voltage range.

What is the role of the TIMER pin in over-current handling?

The TIMER pin implements a timed OCP response: when CS exceeds 0.78 V, a 130 µA current charges the external TIMER capacitor. If voltage reaches 3.5 V, the IC latches off. Recovery requires both TIMER voltage falling below 0.28 V and a full VCC UVLO cycle-ensuring faults are not cleared prematurely.

How is burst mode triggered and what is its impact on efficiency?

Burst mode activates when voltage on the BURST pin falls below 1.23 V (±30 mV hysteresis), causing the IC to halt switching and reduce quiescent current to 1.2 mA. This cuts no-load power consumption significantly-e.g., enabling <0.1 W adapters-while maintaining fast wake-up (<100 µs) when load returns.

What are the absolute maximum ratings for SW and BST pins?

The SW pin withstands –3 V to 600 V with a maximum dV/dt of 50 V/ns; the BST pin handles –0.3 V to 618 V. Exceeding these may damage internal structures. Layout must minimize SW node inductance and use low-ESR/ESL BST capacitors to avoid voltage overshoot beyond 600 V during transients.

Is the HR1001LGS-Z RoHS and halogen-free compliant?

Yes. HR1001LGS-Z is lead-free, halogen-free, and fully compliant with EU RoHS Directive 2011/65/EU. MPS confirms green status on its Quality Assurance portal, and all packaging materials meet IEC 61249-2-21 standards for brominated flame retardants.