Monolithic Power Systems Inc. HR1002AGSE-P

Overview

HR1002AGSE-P from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller with adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), and two-level over-current protection. It delivers 50% duty cycle, variable-frequency control up to 600 kHz, integrates 600V high-side gate driver with bootstrap diode, and operates from 13V–15.5V VCC for high-efficiency AC/DC power supplies in LCD TVs and telecom SMPSs.

For engineers reviewing the HR1002AGSE-P datasheet, HR1002AGSE-P pinout, HR1002AGSE-P application, or HR1002AGSE-P equivalent, this page provides verified functional context, validated pin roles, confirmed protection thresholds (VCS-OCP = 1.5 V, tDMAX = 1.5 µs), and real-world design meaning for ADTA, CMP, and burst-mode operation under light load.

Technical Context

The HR1002AGSE-P implements a modulated current-source oscillator that charges/discharges the CT capacitor between VCFP (3.8 V) and VCFV (0.9 V) to set switching frequency, with FSET providing a precise 2.0 V reference to configure min/max fSW via external resistors RFMIN and RFMAX. Its ADTA circuit senses dV/dt at HBVS to dynamically adjust dead time between HG and LG outputs, ensuring robust zero-voltage switching across line/load transients.

Capacitive mode protection uses dual polarity comparators (VCSPR = 85 mV, VCSNR = −85 mV) triggered after HG/LG turn-off to block subsequent gate drive until slope detection or tCMP (52 µs) expires. Two-level OCP combines frequency-shift regulation (VCS-OCR = 1.0 V) and latched shutdown (VCS-OCP = 1.5 V with VSS-OCP = 1.73 V threshold), coordinated by TIMER pin timing (VTIMER-SD = 3.5 V, ITIMER = 130 µA).

Key Specifications

Pinout & Package

HR1002AGSE-P is housed in an SOIC16-15 package (16-pin, 15 leads, exposed pad not present), with GND on Pin 10 and thermal resistance θJA = 80 °C/W on standard 4-layer PCB.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1002AGSE-P uniquely integrates ADTA, CMP, and configurable burst mode in a single SOIC16-15 package-enabling higher efficiency, smaller magnetics, and robust fault recovery without external circuitry.

Availability

HR1002AGSE-P is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom SMPSs, and AC/DC adapters requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for HR1002AGSE-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over 20 years of expertise in DC/DC, AC/DC, and motor control solutions.

The HR1002A product line targets high-efficiency resonant converters for consumer, telecom, and industrial power supplies, emphasizing adaptive control, integrated protection, and minimal external component count.

FAQ

What is the purpose of the HBVS pin?

The HBVS pin connects a high-voltage capacitor between SW and HBVS to sense dV/dt at the half-bridge switching node. This current signal feeds the Adaptive Dead-Time Adjustment (ADTA) circuit, enabling real-time dead-time control between HG and LG outputs to maintain zero-voltage switching across all operating conditions without manual tuning.

How does capacitive mode protection (CMP) function during a short circuit?

During a short circuit, CMP detects incorrect resonance polarity using VCSPR (85 mV) and VCSNR (−85 mV) thresholds after HG/LG turn-off. It blanks gate drive for tCMP (52 µs), then discharges SS if the condition persists beyond tDMAX (1.5 µs). This prevents hard-switching while allowing controlled burst-mode operation to limit average power and avoid thermal runaway.

Can HR1002AGSE-P operate without an external bootstrap diode?

Yes-HR1002AGSE-P includes an internal bootstrap diode that charges the BST capacitor from VCC to SW. However, an external diode is recommended for faster startup and improved reliability after fault recovery, especially when restarting from deep discharge or high-temperature conditions where internal diode forward voltage drop may delay HG enablement.

What defines the minimum and maximum switching frequencies?

The minimum frequency is set by RFMIN (resistor from FSET to GND), which establishes the lowest current into CT; the maximum frequency is set by RFMAX (resistor from FSET to optocoupler collector), which adds current during regulation. Equations (1) and (2) in the datasheet link fSW to CT capacitance, VCT_HYS (2.85 V), and these resistor values-enabling precise 100–600 kHz tuning.

How is two-level over-current protection implemented?

Level one (OCP regulation) triggers at VCS-OCR = 1.0 V, increasing fSW to limit primary current. If current continues rising past VCS-OCP = 1.5 V while VSS drops below VSS-OCP = 1.73 V, level two (latched shutdown) activates. TIMER pin voltage then rises to VTIMER-SD = 3.5 V, halting switching until VCC is cycled-preventing false trips during surge tests.

Is HR1002AGSE-P compatible with GaN half-bridge MOSFETs?

Yes-its 0.8 A peak HG/LG drive strength, 600V SW rating, and 50V/ns dV/dt immunity support common 600V GaN eHEMTs. The ADTA function is especially valuable with GaN's fast switching, as it dynamically compensates for propagation delays and layout parasitics to maintain robust ZVS across temperature and load.

What is the role of the BO pin in brown-in/brownout protection?

The BO pin monitors bulk input voltage via a resistor divider. When BO voltage exceeds VBO-ON = 2.3 V, the IC enables gate drivers; when it falls below VBO-OFF = 1.81 V, the IC disables. A built-in 5.5 V clamp protects against transient overvoltage, and the hysteresis (0.49 V) prevents oscillation near threshold-ensuring clean startup/shutdown sequencing in universal-input designs.