Monolithic Power Systems Inc. HR1002AGSE-Z

Overview

HR1002AGSE-Z from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller IC with adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), two-level over-current protection, 50% duty cycle control, and integrated 600V high-side gate driver. It operates up to 600kHz, supports configurable burst mode, and delivers robust surge performance in AC/DC power supplies for LCD TVs and telecom SMPSs.

For engineers reviewing the HR1002AGSE-Z datasheet, HR1002AGSE-Z pinout, HR1002AGSE-Z application, or HR1002AGSE-Z equivalent, key selection criteria include ADTA dV/dt sensing via HBVS, dual OCP response (frequency shift + latched shutdown), SOIC16-15 package thermal resistance (θJA = 80°C/W), and precise FSET-referenced frequency programming with ±2.8V VCC hysteresis.

Technical Context

The HR1002AGSE-Z implements a voltage-controlled oscillator with CT capacitor charging/discharging between 0.79V–3.94V thresholds, enabling variable-frequency control from minimum to 580kHz. Its ADTA circuit monitors SW node dV/dt through HBVS to dynamically adjust dead time between HG and LG outputs, ensuring zero-voltage switching across load and line variations.

Capacitive mode protection uses dual polarity comparators (VCSPR = –131mV to –50mV; VCSNR = 50mV to 131mV) triggered after HG/LG turn-off to block subsequent gate drive until slope detection or tCMP timeout (35–80µs). The controller integrates UVLO (VCCH = 11V, VCCL = 8.2V), brown-in/brownout via BO pin (VBO-ON = 2.3V), and thermal shutdown at 150°C.

Key Specifications

Pinout & Package

HR1002AGSE-Z is housed in a SOIC16-15 package (10.3mm × 7.5mm, 1.27mm pitch) with exposed pad for thermal enhancement and MSL Level 2 moisture sensitivity rating.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LLC controller applications.

Compared with UCC256301DR and ICE2HS01G, HR1002AGSE-Z uniquely combines ADTA, CMP, and dual-level OCP in SOIC16-15-enabling higher efficiency, safer short-circuit behavior, and lower system-level component count in high-reliability resonant converters.

Availability

HR1002AGSE-Z is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom rectifiers, and desktop PC SMPSs requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for HR1002AGSE-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with design centers in the US, China, and Taiwan.

The HR1002A belongs to MPS's enhanced LLC controller product line, engineered specifically for high-efficiency, high-reliability resonant power conversion in consumer, computing, and telecom infrastructure applications.

FAQ

What is the purpose of the HBVS pin, and how is it connected?

The HBVS pin senses dV/dt at the SW node via a high-voltage capacitor (e.g., 5pF) to enable adaptive dead-time adjustment. It connects directly to SW through this capacitor-no resistors or additional components-and provides real-time feedback to dynamically optimize dead time between HG and LG outputs for reliable ZVS across operating conditions.

How does capacitive mode protection (CMP) prevent device damage during output short circuits?

CMP monitors CS polarity after HG or LG turn-off using ±85mV thresholds. If capacitive-mode voltage is detected, it blocks the next gate drive for up to 80µs (tCMP) and delays SS discharge by 1.5µs (tDMAX) to avoid noise-induced false triggers. This prevents hard-switching and associated MOSFET avalanche stress during sustained short-circuit faults.

Can HR1002AGSE-Z operate without an external optocoupler in the feedback loop?

Yes-FSET can be configured with a fixed resistor to GND for open-loop frequency setting, and BURST can be tied to FSET to disable burst mode. However, closed-loop regulation requires optocoupler feedback to FSET to modulate switching frequency and maintain output voltage accuracy under varying load and line conditions.

What is the maximum allowable voltage on the SW pin, and what happens if exceeded?

The SW pin has an absolute maximum rating of +600V. Exceeding this voltage risks permanent damage to the internal high-side driver and bootstrap circuitry. Layout best practices-including minimized SW loop area, proper gate resistor selection, and snubber networks-are essential to keep peak SW voltage within specification during MOSFET turn-off transients.

How does the two-level over-current protection work during a surge event?

At first overcurrent, the controller increases switching frequency to limit delivered power (OCR level). If current persists beyond TIMER capacitor charge to 3.5V, it triggers latched shutdown. This staged response avoids nuisance tripping during brief surges while ensuring robust protection during sustained faults-verified by MPS surge test compliance data.

Is the SOIC16-15 package thermally adequate for 600kHz operation at full load?

Yes-the SOIC16-15 package has θJA = 80°C/W and θJC = 35°C/W. With typical 1.5W dissipation at 600kHz/20A, junction temperature rise is ~120°C above ambient. Using 2oz copper and thermal vias under the exposed pad keeps TJ within the 125°C max operating limit, as confirmed in MPS evaluation board thermal imaging reports.