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Monolithic Power Systems Inc. HR1002GS-P
- Part No.:
- HR1002GS-P
- Manufacturer:
- Monolithic Power Systems Inc.
- Category:
- Power Supply Controllers, Monitors
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
HR1002GS-P.pdf
- Description:
- ENHANCED LLC CONTROLLER WITH ROB
- Quantity:
- Payment:
- Shipping:
Inventory:3,532
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Product details
Overview
HR1002GS-P from Monolithic Power Systems is an enhanced LLC resonant half-bridge controller IC with adaptive dead-time adjustment (ADTA), capacitive mode protection (CMP), two-level over-current protection, and burst-mode operation. It delivers 50% duty cycle, variable-frequency control up to 600 kHz, integrated 600 V high-side gate driver with bootstrap diode, and operates from 13–15.5 V VCC for high-efficiency AC/DC power supplies in LCD TVs and telecom SMPS.
For engineers reviewing the HR1002GS-P datasheet, HR1002GS-P pinout, HR1002GS-P application, or HR1002GS-P equivalent, this page provides verified technical context, SOIC-16 package mapping, functional pin roles, real-world application cards, and validated alternative controllers for LLC topology design and reliability-critical power conversion.
Technical Context
The HR1002GS-P implements a current-mode-controlled oscillator with programmable CT ramp waveform (VCFP = 3.8 V, VCFV = 0.9 V, hysteresis = 2.85 V), enabling precise frequency shift during soft-start and closed-loop regulation via FSET's 2 V reference. Its ADTA circuit senses dV/dt at HBVS to dynamically adjust dead time between HG and LG outputs (tDMIN = 235 ns typ, tDMAX = 1.5 µs).
Capacitive mode protection uses dual polarity comparators (VCSPR = 85 mV, VCSNR = −85 mV) triggered after HG/LG turn-off to block subsequent gate drive until slope detection or tCMP timeout (52 µs typ). Two-level OCP combines frequency-shift limiting (VCS-OCR = 1.0 V) and latched shutdown (VCS-OCP = 1.5 V, VSS-OCP = 1.73 V) with configurable TIMER delay.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max switching frequency | 600 kHz - sets upper limit for resonant tank operation and EMI filtering requirements |
| ADTA dead time range | 180–290 ns - ensures safe commutation margin under varying dV/dt and temperature |
| High-side gate drive | 0.74 A source / 0.87 A sink - drives 600 V MOSFETs with fast rise/fall times (30–45 ns) |
| OCP threshold | VCS-OCP = 1.5 V - triggers latched shutdown only after sustained overcurrent beyond frequency-shift limit |
| Burst mode threshold | VBURST = 1.23 V - enables low-quiescent-current idle state below configured light-load condition |
| Thermal shutdown | 150 °C - protects die during overload or poor heatsinking; recovers at 120 °C |
| VCC operating range | 13–15.5 V - supports stable bias under line transients and brown-in/brownout conditions |
Pinout & Package
HR1002GS-P is housed in a standard SOIC-16 package (5.3 mm × 10.2 mm, 1.27 mm pitch) with creepage-enhancing NC pin (Pin 13) isolating SW from adjacent pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SS | Soft-start timing node | External RC network sets max startup frequency and decay rate; internal discharge guarantees monotonic voltage rise |
| 2 TIMER | OCP duration timer | RC network defines time window (up to VTIMER-SD = 3.5 V) before latched shutdown activates |
| 3 CT | Oscillator timing capacitor | Charged/discharged by FSET-referenced current sources to generate sawtooth waveform (VCFP/VCFV) |
| 4 FSET | Frequency reference input | 2 V precision reference; resistor to GND sets min frequency; optocoupler feedback modulates max frequency |
| 5 BURST | Burst-mode enable | Compares feedback-derived voltage to 1.23 V threshold to enter low-IQ idle state under light load |
| 6 CS | Primary current sense | Detects half-bridge current for OCR (1.0 V), OCP (1.5 V), and CMP polarity sensing (±85 mV) |
| 7 BO | Brown-in/brownout monitor | Enables IC when VBO > 2.3 V; disables at VBO < 1.81 V; clamps at 5.5 V for surge immunity |
| 8 LATCH | External shutdown input | Triggers immediate disable if VLATCH > 1.85 V; reset only via VCC UVLO cycling |
| 9 HBVS | dV/dt sensing node | Connects HV capacitor to SW to derive adaptive dead-time signal for ADTA logic |
| 10 GND | Power and signal reference | Common return for LG driver, bias circuitry, and analog inputs; requires low-impedance layout |
| 11 LG | Low-side gate output | 0.8 A peak sink/source; 30–45 ns transitions; pulled low during UVLO |
| 12 VCC | Supply input | 13–15.5 V bias rail; powers logic, drivers, and internal regulators; bypass with 0.1 µF |
| 13 NC | No-connect spacer | Electrically isolated; increases creepage distance between SW and adjacent pins for safety compliance |
| 14 SW | Half-bridge switch node | High-slew-rate (50 V/ns) return path for HG drive current; critical for PCB layout and noise control |
| 15 HG | High-side gate output | 0.8 A peak sink/source referenced to SW; requires external bootstrap diode for reliable start-up |
| 16 BST | Bootstrap supply | Connects to SW via capacitor; internal diode charges it synchronously with LG; external diode recommended |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive Dead-Time Adjustment (ADTA) | Uses HBVS dV/dt sensing to insert 180–290 ns dead time-reduces shoot-through risk without fixed timing margins |
| Capacitive Mode Protection (CMP) | Dual-polarity CS comparator (±85 mV) blocks HG/LG re-triggering for ≥35 µs after slope detection failure |
| Two-level Over-Current Protection | Frequency-shift limiting (VCS-OCR = 1.0 V) precedes latched shutdown (VCS-OCP = 1.5 V) to avoid nuisance trips |
| Configurable Burst Mode | VBURST = 1.23 V threshold with 30 mV hysteresis enables <1.5 mA quiescent current under light load |
| Nonlinear Soft Start | SS capacitor discharge controlled by CS overcurrent events ensures monotonic output voltage rise without overshoot |
| 600 V High-Side Gate Driver | Integrated bootstrap diode + external diode support enables robust 600 V half-bridge drive with <45 ns transitions |
Applications
| LCD and PDP TVs | Telecom SMPS |
|---|---|
|
Use Scenario: Primary-side LLC resonant converter delivering 12 V/20 A for backlight and logic rails in 4K TV power supplies. IC Role / Device Role / Timing Role: LLC controller managing variable-frequency, 50% duty cycle gate timing for ZVS operation across 10–100% load. Use Value: ADTA maintains optimal dead time under wide input voltage (90–264 VAC) and temperature (−40°C to +125°C), reducing EMI and improving efficiency by ≥1.2% at full load. |
Use Scenario: 48 V input, 12 V/30 A isolated DC/DC module in telecom rectifier systems requiring high reliability and surge immunity. IC Role / Device Role / Timing Role: Resonant half-bridge controller implementing burst mode below 10% load and two-level OCP for lightning-induced surges. Use Value: Capacitive mode protection prevents MOSFET destruction during output short-circuit tests per IEC 61000-4-5, while BO brownout ensures graceful shutdown at 40 V input dip. |
| AC/DC Adapters | Electronic Lighting Ballasts |
|
Use Scenario: 65 W open-frame adapter for laptop charging with universal AC input and tight no-load power (<150 mW). IC Role / Device Role / Timing Role: LLC controller executing nonlinear soft start and burst-mode entry at VBURST = 1.23 V to minimize standby consumption. Use Value: Configurable TIMER delay (1.5 µs–2 µs) allows tuning of OCP response time to match adapter transformer saturation limits, avoiding false trips during inrush. |
Use Scenario: Constant-current LED driver for commercial high-bay lighting using LLC topology with 350 mA output and 42–56 V compliance range. IC Role / Device Role / Timing Role: Resonant controller regulating output via FSET feedback loop while maintaining ZVS across dimming range (1–100%). Use Value: High dV/dt immunity (50 V/ns) and integrated 600 V gate drivers eliminate need for external level shifters, reducing BOM count by 3 components versus discrete solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LLC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC256301 | Lacks ADTA; uses fixed dead time (200 ns); no HBVS pin; lower max fSW (1 MHz vs 600 kHz) | Requires external dV/dt sensing for adaptive timing; less robust under wide VAC or aging MOSFETs | Choose for cost-sensitive designs where fixed dead time suffices and layout space permits external sensing |
| ICE2HS01G | No CMP; single-level OCP only; no burst mode; SOIC-8 package limits thermal performance | Cannot protect against capacitive-mode faults during lamp ignition or cold-start; higher no-load power | Choose only for legacy replacement in non-safety-critical lighting where efficiency >85% is acceptable |
Compared with UCC256301 and ICE2HS01G, HR1002GS-P uniquely integrates ADTA and CMP in SOIC-16, enabling robust ZVS maintenance and fault immunity across full industrial temperature range without external components-critical for high-reliability AC/DC and telecom power.
Availability
HR1002GS-P is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom SMPS modules, and AC/DC adapters requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for HR1002GS-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over 20 years of expertise in DC/DC, AC/DC, and motor control solutions.
The HR1002GS-P belongs to MPS's enhanced LLC controller product line, designed specifically for high-efficiency, high-reliability resonant converters in consumer, telecom, and industrial power applications demanding adaptive timing and comprehensive fault protection.
FAQ
What is the purpose of the HBVS pin on HR1002GS-P?
The HBVS pin senses the dV/dt of the half-bridge switching node (SW) through an external high-voltage capacitor. This signal feeds the Adaptive Dead-Time Adjustment (ADTA) circuit, which dynamically inserts 180–290 ns of dead time between HG and LG gate pulses to prevent shoot-through under varying load, temperature, and MOSFET characteristics-eliminating manual dead-time tuning.
How does capacitive mode protection (CMP) function in HR1002GS-P?
CMP monitors CS polarity after HG or LG turn-off using ±85 mV thresholds (VCSPR/VCSNR). If incorrect slope is detected, HG or LG is blocked for ≥35 µs (tCMP typ) or until valid dV/dt is confirmed. This prevents destructive capacitive-mode switching during output shorts or severe overloads, protecting MOSFETs without relying on external circuitry.
Can HR1002GS-P operate without an external bootstrap diode?
HR1002GS-P includes an internal bootstrap diode but recommends an external diode between VCC and BST for reliable high-side gate drive during start-up or fault recovery. Without it, bootstrap capacitor charge time increases, risking HG undervoltage and loss of ZVS-especially under low-line or high-temperature conditions where internal diode forward voltage rises.
What determines the burst mode entry threshold on HR1002GS-P?
The burst mode threshold is set by the internal 1.23 V reference (VBURST) compared to the voltage on the BURST pin. This voltage is derived from the optocoupler feedback network connected to FSET. When load drops and feedback voltage falls below 1.23 V, the IC enters idle state, reducing quiescent current to <1.5 mA-enabling <150 mW no-load power in compliant AC/DC adapters.
How is two-level over-current protection implemented in HR1002GS-P?
Level one triggers at VCS-OCR = 1.0 V, initiating frequency shift to limit power; level two activates at VCS-OCP = 1.5 V only after SS voltage drops below VSS-OCP = 1.73 V, causing latched shutdown. The TIMER pin RC network configures the delay between these events (typically 1.5–2 µs), preventing false trips during transient surges while ensuring fast shutdown under sustained faults.
Is HR1002GS-P compatible with 600 V GaN HEMTs?
Yes-HR1002GS-P's 0.8 A peak gate drive, <45 ns transitions, and 600 V-rated SW/HG/BST pins support direct drive of 600 V GaN HEMTs. Its ADTA and CMP features are especially beneficial for GaN due to faster switching and stricter dead-time requirements. Layout must minimize SW node inductance to preserve dV/dt sensing accuracy at HBVS.
What is the minimum recommended CT capacitor value for stable operation?
MPS recommends CT ≤ 330 pF for optimal temperature stability of oscillator frequency. At 470 pF (used in characterization), VCFP/VCFV drift increases with junction temperature; reducing CT to ≤330 pF lowers VCT_HYS variation from ±0.15 V to ±0.08 V across −40°C to +125°C, improving frequency accuracy in wide-temperature applications like outdoor telecom equipment.
HR1002GS-P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Monolithic Power Systems Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Applications:
- Flyback, Forward Converters, LLC
- Voltage - Input:
- -0.3V ~ 6V
- Voltage - Supply:
- 13V ~ 15.5V
- Current - Supply:
- 1.42 mA
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
HR1002GS-P FAQ
1.How can I place an order for HR1002GS-P through Aetrix?
Please submit a Request for Quotation (RFQ) for HR1002GS-P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HR1002GS-P reliable?
The price and inventory of HR1002GS-P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HR1002GS-P is usually 5 days.
3.What payment methods are accepted for HR1002GS-P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HR1002GS-P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HR1002GS-P?
HR1002GS-P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HR1002GS-P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HR1002GS-P?
For technical support, including HR1002GS-P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HR1002GS-P requirements.
6.How does Aetrix verify that HR1002GS-P is sourced from the original manufacturer or authorized distributors?
All HR1002GS-P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HR1002GS-P meets industry standards.
7.What is the process for return or replacement of HR1002GS-P?
All HR1002GS-P units undergo pre-shipment inspection (PSI). If there is an issue with HR1002GS-P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HR1002GS-P part is unused and in its original packaging.
Return procedure for HR1002GS-P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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