Renesas IDT72V90823BC

Overview

IDT72V90823 from Integrated Device Technology is a 3.3 V, 2,048 × 2,048 non-blocking time slot interchange (TSI) digital switch optimized for ST-BUS®/GCI and wide frame pulse (WFP) telecommunication interfaces. It supports serial data rates of 2.048 Mb/s, 4.096 Mb/s, or 8.192 Mb/s with per-channel variable or constant throughput delay, 5V-tolerant I/O, and IEEE-1149.1 JTAG test port - deployed in carrier-grade TDM switching systems requiring precise channel-level timing control.

For engineers reviewing the IDT72V90823 datasheet, IDT72V90823 pinout, IDT72V90823 application, or IDT72V90823 equivalent, key selection considerations include frame alignment mode (ST-BUS®/GCI vs. WFP), per-channel delay configuration (V/C bit), microprocessor interface mode (multiplexed/non-multiplexed), input offset calibration via FE/HCLK, and 5V-tolerant TX/RX stream I/O compatibility with legacy 5V logic domains.

Technical Context

The IDT72V90823 implements a dual-mode serial interface: ST-BUS®/GCI auto-detection (via F0i polarity analysis) and WFP frame alignment (enabled by WFPS = HIGH), each with distinct CLK, FE/HCLK, and frame pulse timing requirements. Its internal architecture includes parallelized serial-to-parallel converters, 8 KB configurable data memory, and connection memory with per-channel control bits (V/C, LPBK, PC, OSB, CCO).

Switching operation is governed by connection memory mapping: in Connection Mode, source addresses (CAB/SAB) route data from data memory to TX outputs; in Processor Mode, direct write-to-output bypasses data memory. Throughput delay is programmable per channel - variable mode achieves minimum 3-time-slot latency; constant mode guarantees fixed 1-frame delay using multi-buffer staging for frame integrity in concatenated data streams.

Key Specifications

Pinout & Package

Package: 100-pin Ball Grid Array (BGA), 1mm pitch, 11mm × 11mm footprint (order code BC100-1). Pinout conforms to IDT's BC variant - all power (VCC/GND), serial I/O (RX0–15/TX0–15), microprocessor interface (AD0–7/D8–15/A0–7/CS/DS/RD/R/W/AS/ALE/IM), and control signals (CLK/FE/HCLK/F0i/WFPS/ODE/RESET/TRST/TCK/TMS/TDI/TDO/CCO/DTA) are fully assigned per datasheet Figure 2 and Pin Description Table.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar time slot interchange applications.

Compared with IDT72V90822 and CY7C9252, the IDT72V90823 uniquely delivers full 2,048 × 2,048 non-blocking switching at 8.192 Mb/s with 5V-tolerant I/O, WFP mode, and IEEE-1149.1 JTAG - making it the sole option for scalable carrier-class TDM switching requiring backward-compatible 5V logic integration and multi-chip frame alignment.

Availability

IDT72V90823 is available at Aetrix Electronics and suitable for telecom access concentrators, digital loop carriers, VoIP gateways, and TDM-over-IP edge switches requiring stable component supply across extended product lifecycles.

Supply support for IDT72V90823 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT) was a fabless semiconductor company specializing in timing, memory interface, RF, and communications ICs before its acquisition by Renesas in 2019. IDT pioneered high-density TSI solutions for carrier infrastructure.

The IDT72V90823 belongs to IDT's 72V family of time slot interchange switches, designed specifically for scalable, low-latency TDM switching in E1/T1 access networks, DSLAMs, and multi-service provisioning platforms.

FAQ

What is the maximum serial data rate supported by the IDT72V90823?

The IDT72V90823 supports a maximum serial data rate of 8.192 Mb/s, achieved when DR0=0 and DR1=1 in the IMS register. At this rate, it delivers full 2,048 × 2,048 non-blocking channel capacity with 128 time-slots per frame and requires a 16.384 MHz master clock (CLK). Lower rates - 4.096 Mb/s (1,024 × 1,024) and 2.048 Mb/s (512 × 512) - are also supported via DR bit configuration.

How does the IDT72V90823 handle frame synchronization for ST-BUS® versus GCI interfaces?

The IDT72V90823 automatically detects ST-BUS® or GCI frame format by analyzing the polarity and edge behavior of the F0i input signal. In ST-BUS® mode, it locks to the falling edge of F0i and clocks data on the rising edge of CLK; in GCI mode, it uses the rising edge of F0i and clocks data on CLK's falling edge. This auto-detection occurs at power-up or after reset and requires no software configuration.

Can the IDT72V90823 operate with a 5V microprocessor interface while using a 3.3V supply?

Yes - the IDT72V90823 features 5V-tolerant I/O on all microprocessor interface pins (AD0–7, D8–15, A0–7, CS, DS/RD, R/W/WR, AS/ALE, IM), allowing direct connection to 5V CPUs or logic without level shifters. The core VCC remains at 3.3V, and internal protection circuitry ensures safe operation under 5V input conditions per datasheet Note 3.

What is the purpose of the CCO pin on the IDT72V90823?

The CCO (Connection Control Output) pin outputs a serial bitstream derived from the CCO bit in each connection memory location, synchronized to the active data rate (4.096/8.192/16.384 Mb/s). It transmits one bit per time-slot, positioned one slot ahead of the corresponding TX output - enabling real-time sideband signaling for downstream devices such as channel banks or framer ICs.

How is input frame offset delay measured and compensated on the IDT72V90823?

Input frame offset delay is measured using the FE/HCLK pin in ST-BUS®/GCI mode: asserting the SFE bit initiates a two-frame evaluation cycle, after which the FAR register contains a 12-bit offset value. This value is then written to the Frame Input Offset Register (FOR) for the target RX stream, applying up to ±4.5 CLK-period correction with 0.5-cycle resolution to align skewed input frames.