Renesas IDT72V90823J

Overview

IDT72V90823 from Integrated Device Technology is a 3.3 V, 2,048 × 2,048 non-blocking time slot interchange (TSI) digital switch for ST-BUS®/GCI and wide frame pulse (WFP) interfaces. It supports serial data rates of 2.048 Mb/s, 4.096 Mb/s, or 8.192 Mb/s with per-channel variable or constant throughput delay, IEEE-1149.1 JTAG test port, and 5V-tolerant I/O - deployed in telecom voice/data multiplexing systems.

For engineers reviewing the IDT72V90823 datasheet, IDT72V90823 pinout, IDT72V90823 application, or IDT72V90823 equivalent, key selection considerations include frame alignment mode (ST-BUS®/GCI vs. WFP), microprocessor interface configuration (multiplexed/non-multiplexed), per-channel high-impedance control via ODE and connection memory, input frame offset calibration, and 3.3 V supply with commercial temperature range (–40°C to +85°C).

Technical Context

The IDT72V90823 implements a dual-mode serial interface: ST-BUS®/GCI with automatic frame format detection (F0i polarity sensing), or WFP mode enabled by WFPS = HIGH requiring 4.096 MHz HCLK and 16.384 MHz CLK. Its internal architecture includes parallelized serial-to-parallel/parallel-to-serial converters, 8 KHz frame-synchronized data memory (up to 2,048 bytes), and configurable connection memory with five per-channel control bits (PC, V/C, OE, LPBK, CCO).

Switching operation occurs in either Connection Mode (source addresses in connection memory route data from data memory to TX outputs) or Processor Mode (microprocessor writes direct output data to connection memory). Delay behavior is programmable per channel: variable delay (min. 3 time-slots, optimized for voice) or constant delay (1-frame minimum, preserves frame integrity for concatenated data).

Key Specifications

Pinout & Package

Package: 84-pin Plastic Leaded Chip Carrier (PLCC), 0.05″ pitch, 1.15″ × 1.15″ (order code J). Pin 1 marked by index corner; IC pin must be tied to GND for normal operation and IEEE 1149 compliance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar time slot interchange applications.

Compared with IDT72V90822 and CY7C9252, the IDT72V90823 uniquely delivers full 2,048 × 2,048 non-blocking capacity at 8.192 Mb/s with automatic interface detection and WFP support - making it the sole option for scalable, future-proof ST-BUS®/GCI gateway designs requiring zero-configuration frame alignment.

Availability

IDT72V90823 is available at Aetrix Electronics and suitable for telecom infrastructure, digital loop carrier systems, and voice-over-IP gateway designs requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for IDT72V90823 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT) was a fabless semiconductor company specializing in timing, memory interface, RF, and communications ICs before its acquisition by Renesas Electronics in 2019. IDT pioneered high-density TSI switches for digital telephony.

The IDT72V90823 belongs to IDT's time slot interchange (TSI) product line, designed specifically for carrier-class voice/data multiplexing in ST-BUS®, GCI, and WFP-based telecom systems - emphasizing low-latency switching, frame integrity, and flexible microprocessor integration.

FAQ

What is the maximum serial data rate supported by the IDT72V90823?

The IDT72V90823 supports a maximum serial data rate of 8.192 Mb/s, achieved when DR0=0 and DR1=1 in the IMS register. At this rate, the device operates with 16 input and 16 output streams, each carrying 128 × 64 kbit/s channels in 125 µs frames, requiring a 16.384 MHz master clock (CLK) input. Lower rates of 4.096 Mb/s and 2.048 Mb/s are also supported with corresponding scaling of channel count and clock frequency.

How does the IDT72V90823 handle frame synchronization for mixed ST-BUS® and GCI interfaces?

The IDT72V90823 automatically detects and adapts to ST-BUS® or GCI frame formats on the F0i input by sensing signal polarity and edge transitions. In ST-BUS® mode, it samples data on the rising edge of CLK three-quarters into the bit cell with falling-edge frame alignment; in GCI mode, it uses the falling edge of CLK and rising-edge frame alignment. This detection occurs at power-up or reset and requires no software configuration - a core capability of the IDT72V90823.

Can the IDT72V90823 operate in both Connection Mode and Processor Mode simultaneously?

No - the IDT72V90823 operates exclusively in either Connection Mode or Processor Mode per output channel, controlled by the PC (Processor Channel) bit in each location of the connection memory. When PC = 0, the channel routes data from data memory using source address bits (SAB/CAB); when PC = 1, the channel outputs the value written directly to that connection memory location. Both modes coexist across different channels but are not mixed within a single channel's operation.

What is the function of the ODE pin on the IDT72V90823, and how does it interact with per-channel control?

The ODE (Output Drive Enable) pin is an active-low global enable for all TX0–TX15 serial output drivers. When ODE = LOW and the OSB bit in the IMS register is LOW, all TX outputs enter high-impedance state - overriding individual per-channel OE bits. When ODE = HIGH, per-channel OE bits in the connection memory determine driver state. This dual-level control allows both system-level shutdown (e.g., during power sequencing) and fine-grained channel muting in the IDT72V90823.

Is the IDT72V90823 compatible with 5 V microprocessor buses?

Yes - all I/O pins except TMS, TDI, and TRST are 5V tolerant, enabling direct interfacing with 5 V microprocessors or FPGAs without level-shifting circuitry. The IDT72V90823 itself operates from a 3.3 V supply, and its internal logic levels are 3.3 V, but the input buffers accept 0–5.5 V signals safely. This tolerance simplifies integration into mixed-voltage telecom control planes while maintaining low-power 3.3 V core operation in the IDT72V90823.