Renesas IDT72V90823J8

Overview

IDT72V90823 from Integrated Device Technology is a 3.3 V, 2,048 × 2,048 non-blocking time slot interchange (TSI) digital switch optimized for ST-BUS®/GCI and wide frame pulse (WFP) telecommunication interfaces. It supports serial data rates of 2.048 Mb/s, 4.096 Mb/s, or 8.192 Mb/s with per-channel variable or constant throughput delay, JTAG boundary scan (IEEE-1149.1), and 5V-tolerant I/O - deployed in carrier-grade TDM switching systems requiring precise channel-level timing control.

For engineers reviewing the IDT72V90823 datasheet, IDT72V90823 pinout, IDT72V90823 application, or IDT72V90823 equivalent, key selection criteria include its 84-pin PLCC package (order code J), 3.3 V supply with -40°C to +85°C operation, per-stream frame offset calibration, Processor/Connection mode flexibility, and support for both Motorola and Intel-style microprocessor interfaces.

Technical Context

The IDT72V90823 implements a dual-mode TSI architecture with separate data memory (up to 2,048 bytes) and connection memory (16 streams × 128 channels × 16 bits), enabling per-channel routing decisions via CAB/SAB addressing or direct processor-write data injection. Its timing unit synchronizes to F0i (8 kHz frame pulse) and CLK (4.096–16.384 MHz), with automatic ST-BUS®/GCI format detection based on FE/HCLK edge polarity.

Frame alignment evaluation uses the FE input to measure input stream skew against F0i, storing 12-bit offset values in FOR registers; delay compensation is applied before data enters the parallel-to-serial converters. The CCO output delivers connection memory control bits at the same bit rate as TX/RX streams, synchronized one time-slot ahead for deterministic control signaling.

Key Specifications

Pinout & Package

Package: 84-pin Plastic Leaded Chip Carrier (PLCC), 0.05-inch pitch, 1.15-inch × 1.15-inch footprint (order code J). Pin 1 marked by index notch; IC pin must be tied to GND for normal operation and IEEE-1149.1 compliance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar time slot interchange applications.

Compared with IDT72V90813J8 and CY7C9252-10JC, the IDT72V90823 uniquely delivers full 2K×2K non-blocking capacity at 8.192 Mb/s with integrated WFP support, per-stream frame offset calibration, and JTAG testability - making it the sole option for scalable, standards-compliant carrier-class TDM switching.

Availability

IDT72V90823 is available at Aetrix Electronics and suitable for telecom line card development, carrier-grade access multiplexer production, and SONET/SDH add-drop multiplexer design requiring stable component supply across extended product lifecycles.

Supply support for IDT72V90823 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT) was a fabless semiconductor company specializing in timing, memory interface, RF, and high-performance interconnect solutions before its acquisition by Renesas Electronics in 2019.

The IDT72V90823 belongs to IDT's TSI digital switch family, engineered specifically for carrier-class TDM infrastructure requiring deterministic time-slot routing, multi-rate frame alignment, and IEEE-1149.1 testability in commercial temperature environments.

FAQ

What is the maximum serial data rate supported by the IDT72V90823?

The IDT72V90823 supports a maximum serial data rate of 8.192 Mb/s, enabling 2,048 × 2,048 non-blocking time-slot interchange. At this rate, the device requires a 16.384 MHz master clock (CLK), operates with 128 time-slots per 125 µs frame, and achieves full switching capacity. Lower rates - 4.096 Mb/s (1,024 × 1,024) and 2.048 Mb/s (512 × 512) - are also supported with corresponding clock and frame configurations. The IDT72V90823 automatically adapts internal timing and memory addressing based on DR0/DR1 bits in the IMS register.

How does the IDT72V90823 handle frame synchronization for ST-BUS® and GCI interfaces?

The IDT72V90823 automatically detects and configures for ST-BUS® or GCI frame formats using the F0i input and FE/HCLK pin. In ST-BUS® mode, it samples on the rising edge of CLK three-quarters into the bit cell with falling-edge frame alignment; in GCI mode, it samples on the falling edge of CLK with rising-edge frame alignment. This detection occurs at power-up or reset and requires no software configuration - the IDT72V90823 internally evaluates edge polarity and sets appropriate sampling windows for error-free frame boundary tracking.

Can the IDT72V90823 operate in both Processor Mode and Connection Mode simultaneously?

No, the IDT72V90823 operates in either Processor Mode or Connection Mode on a per-channel basis, controlled by the PC (Processor Channel) bit in each connection memory location. When PC = 1, the contents of that memory location are output directly on the corresponding TX stream; when PC = 0, the CAB and SAB bits define the source address from data memory. Both modes coexist within the same device but are resolved per channel during each time-slot - enabling hybrid configurations such as processor-controlled signaling channels alongside connection-mode voice paths.

What is the function of the CCO pin on the IDT72V90823?

The CCO (Control Output) pin on the IDT72V90823 serially outputs the CCO bit from each connection memory location at the same bit rate as the TX/RX streams - 4.096 Mb/s, 8.192 Mb/s, or 16.384 Mb/s - delivering 512, 1,024, or 2,048 bits per frame respectively. It transmits one time-slot ahead of the associated channel (e.g., CCO bit from TX0, CH0 appears during CH31 of the same frame in 2.048 Mb/s mode), providing deterministic sideband control signaling synchronized to the TSI data path without requiring additional interface resources.

Is the IDT72V90823 pin-compatible with other devices in the IDT72V90xx family?

No, the IDT72V90823 is not pin-compatible with other members of the IDT72V90xx family. While functional similarities exist (e.g., IDT72V90813J8 shares the same PLCC-84 package), pin assignments differ significantly - particularly for control signals like WFPS, IM, and CCO, and for memory interface lines. The IDT72V90823 introduces WFP mode support, expanded connection memory, and enhanced frame evaluation logic not present in earlier variants, resulting in incompatible pin mapping. Board-level reuse requires redesign of microprocessor interface and serial I/O routing.