Renesas IDT72V90823JG

Overview

IDT72V90823 from Integrated Device Technology is a 3.3 V, 2,048 × 2,048 non-blocking time slot interchange (TSI) digital switch optimized for ST-BUS®/GCI and wide frame pulse (WFP) telecommunication interfaces. It supports serial data rates of 2.048 Mb/s, 4.096 Mb/s, or 8.192 Mb/s with per-channel variable or constant throughput delay, JTAG boundary scan (IEEE-1149.1), and 5V-tolerant I/O. It is used in TDM-based voice/data switching systems including digital PBX, access multiplexers, and SS7 signaling gateways.

For engineers reviewing the IDT72V90823 datasheet, IDT72V90823 pinout, IDT72V90823 application, or IDT72V90823 equivalent, key selection considerations include its 84-pin PLCC (J) package compatibility, per-stream frame offset calibration, microprocessor interface flexibility (Intel/Motorola multiplexed/non-multiplexed), and support for both ST-BUS®/GCI auto-detection and WFP alignment modes.

Technical Context

The IDT72V90823 implements a dual-mode serial interface: ST-BUS®/GCI with automatic format detection via F0i and FE/HCLK, and WFP mode enabled by WFPS = HIGH requiring 16.384 MHz CLK and 4.096 MHz HCLK. Its internal architecture includes 8 KHz frame-aligned data memory (up to 2,048 bytes), connection memory with per-channel control bits (PC, V/C, LPBK, OE, CCO), and parallel-to-serial/serial-to-parallel converters synchronized to CLK.

Switching operation is controlled through two primary modes: Connection Mode (source address mapping from data memory) and Processor Mode (direct write to TX streams). Delay behavior is configurable per channel - variable delay (min. 3 time-slots) preserves minimum voice latency, while constant delay (1-frame minimum) ensures frame integrity for concatenated data channels.

Key Specifications

Pinout & Package

Available in 84-pin Plastic Leaded Chip Carrier (PLCC), order code J. Pin 1 marked by index corner; IC pin must be tied to GND for normal operation and IEEE-1149.1 compliance. All I/O pins are 5V tolerant except TMS, TDI, and TRST.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar time slot interchange applications.

Compared with IDT72V90822 and CY22393, the IDT72V90823 uniquely delivers full 2,048 × 2,048 non-blocking switching with WFP/ST-BUS® dual-mode support, per-channel loopback, and frame offset calibration - making it irreplaceable in carrier-grade TDM fabric designs requiring scalability, diagnostics, and multi-standard interoperability.

Availability

IDT72V90823 is available at Aetrix Electronics and suitable for digital PBX core switching, SS7 signaling gateways, DSLAM line card aggregation, and wireless base station controllers requiring stable component supply across extended product lifecycles.

Supply support for IDT72V90823 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT) was a fabless semiconductor company specializing in timing, memory interface, RF, and high-performance interconnect solutions before its acquisition by Renesas Electronics in 2019.

The IDT72V90823 belongs to IDT's TSI digital switch product line, designed specifically for carrier-class TDM infrastructure requiring precise frame-aligned switching, multi-standard interface support, and field-diagnostic capabilities in telecom line cards and access equipment.

FAQ

What is the maximum serial data rate supported by the IDT72V90823?

The IDT72V90823 supports a maximum serial data rate of 8.192 Mb/s, enabling 2,048 × 2,048 non-blocking channel switching with 128 time-slots per 125 µs frame. At this rate, the required master clock (CLK) is 16.384 MHz. Lower configurations include 4.096 Mb/s (1,024 × 1,024) and 2.048 Mb/s (512 × 512), each with corresponding CLK frequencies of 8.192 MHz and 4.096 MHz respectively.

Does the IDT72V90823 support both ST-BUS® and GCI interface standards?

Yes, the IDT72V90823 automatically detects and configures itself for either ST-BUS® or GCI framing formats when the WFPS pin is LOW. It identifies frame polarity and bit-clock edge alignment (rising vs. falling) on the F0i input without software configuration, ensuring seamless interoperability with Mitel-compatible and generic GCI-based TDM systems.

How does the IDT72V90823 handle frame synchronization skew across multiple input streams?

The IDT72V90823 provides per-stream frame input offset calibration using the FE/HCLK pin and frame input offset registers (FOR). Each RX stream can be individually delayed up to +4.5 CLK periods in 0.5-cycle increments to compensate for PCB trace length mismatches or backplane propagation delays - critical for maintaining channel alignment in distributed switch fabrics.

Can the IDT72V90823 operate in a microprocessor interface mode compatible with Intel 8086-style buses?

Yes, the IDT72V90823 supports Intel-style multiplexed bus operation when the IM pin is HIGH and appropriate timing (RD/WR, AD0–AD7, ALE) is applied. The DS/RD pin functions as RD (active LOW), and R/W/WR functions as WR (active LOW), allowing direct connection to 8086/8088 and compatible microprocessors without external bus translators.

What is the function of the CCO pin on the IDT72V90823?

The CCO (Control Clock Output) pin outputs the CCO bit from each connection memory location sequentially at the selected serial data rate - 512 bits/frame at 2.048 Mb/s, 1,024 bits/frame at 4.096 Mb/s, or 2,048 bits/frame at 8.192 Mb/s. It is synchronous with TX streams and outputs one time-slot ahead, enabling external monitoring of per-channel control states such as loopback or processor mode activation.