Renesas IDT79R4700-133G

Overview

IDT79R4700-133G from Integrated Device Technology is a 64-bit RISC microprocessor implementing the MIPS-III ISA, operating at 133 MHz with 16 KB instruction and 16 KB data caches, 64-bit integer and floating-point units, and full software/pin compatibility with the R4XXX family. It targets high-performance embedded networking and printing systems requiring deterministic real-time execution and large virtual address space.

For engineers reviewing the IDT79R4700-133G datasheet, IDT79R4700-133G pinout, IDT79R4700-133G application, or IDT79R4700-133G equivalent, key selection criteria include its 133 MHz clock speed, 64 GB physical address space, 5-stage pipeline latency, TLB lock capability for real-time systems, and dual-voltage support (5 V core / 3.3 V I/O).

Technical Context

The IDT79R4700-133G implements a simple 5-stage integer pipeline with fully bypassed register file and autonomous multiply/divide unit, enabling single-cycle ALU operations and precise exception handling. Its floating-point co-processor supports IEEE 754 single/double precision arithmetic with pipelined multiply (4-cycle initiation) and 61-cycle double-precision divide latency.

Virtual memory is managed via a 96-entry fully associative Joint TLB, two-entry ITLB, and four-entry DTLB - all supporting per-page cache coherency attributes and configurable page sizes (4 KB to 16 MB). The MMU enables kernel/supervisor/user modes with distinct 1024 GB, 256.5 GB, and 256 GB virtual address spaces respectively in 64-bit mode.

Key Specifications

Pinout & Package

Package: 208-pin QFP (Plastic Quad Flat Pack), cavity-down thermal construction rated for 0°C to +85°C case temperature.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 64-bit RISC microprocessor applications.

Compared with IDT79R4650-133G, the IDT79R4700-133G delivers integrated floating-point capability and doubled cache size for improved throughput in mixed workload environments; versus IDT79R5000-150G, it offers lower power and simpler thermal management at the expense of peak frequency and cache density.

Availability

IDT79R4700-133G is available at Aetrix Electronics and suitable for LAN switches, enterprise routers, color laser printers, and industrial protocol gateways requiring stable component supply across extended product lifecycles.

Supply support for IDT79R4700-133G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT) was a fabless semiconductor company specializing in timing, memory interface, RF, and embedded processor solutions before its acquisition by Renesas Electronics in 2019.

The IDT79R4700-133G belongs to IDT's RC4700 processor family, designed specifically for high-performance embedded networking and printing applications demanding MIPS-III compatibility, deterministic real-time behavior, and scalable memory architecture.

FAQ

What is the maximum operating temperature specification for the IDT79R4700-133G?

The IDT79R4700-133G is guaranteed for operation at a case temperature range of 0°C to +85°C. This rating applies to both the 208-pin QFP and 179-pin PGA packages. Thermal resistance (∅CA) varies with airflow - for example, 7°C/W at 200 ft/min for QFP - so board-level cooling must be designed to maintain case temperature within limits under worst-case power dissipation. The IDT79R4700-133G does not include on-die thermal sensors; system-level monitoring is required.

Does the IDT79R4700-133G support little-endian or big-endian byte ordering?

The IDT79R4700-133G supports both endianness modes, selected at boot time via bit 8 of the serial mode stream: '0' configures little-endian, '1' configures big-endian. This setting is latched at reset and remains fixed during runtime. The IDT79R4700-133G does not support dynamic endianness switching. Firmware must be compiled for the selected mode, as instruction fetch and data load/store behavior depend on this configuration.

How does the TLB locking feature work in the IDT79R4700-133G?

The IDT79R4700-133G implements TLB locking via the CP0 Wired register, which defines the number of lowest-index JTLB entries immune to random replacement. When a TLB miss occurs, locked entries are never overwritten, ensuring critical kernel mappings (e.g., interrupt vectors, page tables) remain resident. The IDT79R4700-133G does not support per-entry lock bits; locking is contiguous from entry 0 upward. This mechanism guarantees bounded TLB miss latency for real-time interrupt service routines.

Can the IDT79R4700-133G execute instructions from external memory without caching?

Yes, the IDT79R4700-133G supports uncached execution via kseg1 (uncached kernel physical address space), mapped to addresses 0xA0000000–0xBFFFFFFF in 32-bit mode. Instructions fetched from this region bypass the 16 KB instruction cache and are executed directly from external memory. This mode is used for boot ROM, diagnostic code, or memory-mapped peripherals where cache coherency cannot be guaranteed. The IDT79R4700-133G does not support disabling the cache globally - only region-based uncached access.

What boot-time configuration options affect the system interface timing of the IDT79R4700-133G?

Boot-time mode bits 10:9 select the write protocol (R4000-compatible, pipelined writes, or write re-issue), directly impacting SysAD bus utilization efficiency. Bits 7:5 configure the clock divisor for TClock/RClock outputs, determining external bus frequency. Bit 8 sets endianness, affecting data alignment in multi-byte transfers. These settings are loaded from a 256-bit serial stream at power-on and define the fundamental electrical and protocol behavior of the IDT79R4700-133G's system interface before any code execution begins.