Renesas IDT79RC32T351-100DH

Overview

IDT79RC32T351-100DH from Integrated Device Technology is a 32-bit communications processor integrating RC32300 MIPS-II core, dual 16550-compatible UARTs, SDRAM controller (2 banks, 512 MB total), 10/100 Ethernet MAC with MII, USB 1.1 device controller, ATM SAR engine, and 14-channel DMA. It operates at up to 100 MHz pipeline frequency with 2.5 V core / 3.3 V I/O supply and targets xDSL residential gateways and SOHO routers.

For engineers reviewing the IDT79RC32T351-100DH datasheet, IDT79RC32T351-100DH pinout, IDT79RC32T351-100DH application, or IDT79RC32T351-100DH equivalent, key selection criteria include integrated ATM SAR support, UTOPIA Level 1/2 configurability, EJTAG real-time trace capability, and SODIMM compatibility for compact embedded networking designs.

Technical Context

The IDT79RC32T351-100DH implements a hybrid ATM SAR architecture where hardware handles CRC-32/AAL5, HEC, cell buffering (16 cells), and UTOPIA timing, while software manages higher-layer segmentation and reassembly-enabling flexible xDSL modem or Layer 3 switch line card deployment. Its RC32300 CPU core executes DSP instructions for 33.6/56 kbps modem emulation and uses per-line cache locking to guarantee real-time latency for critical protocol stacks.

Memory subsystem includes a 26-bit address/32-bit data peripheral bus supporting Flash, SRAM, and dual-port memory with Intel/Motorola-style wait-state generation, plus dedicated SDRAM controller with automatic refresh, page-mode optimization, and 32-bit data path-delivering up to 200 MB/s peak bandwidth. The 14-channel descriptor-based DMA supports unaligned scatter/gather transfers across memory, Ethernet, USB, and ATM interfaces without CPU intervention.

Key Specifications

Pinout & Package

Package: 208-pin Plastic Quad Flat Package (PQFP), 28 × 28 mm, 0.65 mm pitch, RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar communications processor applications.

Compared with LSI L64200-SC and Intel IXP425, the IDT79RC32T351-100DH uniquely combines programmable MIPS CPU, hardware-assisted ATM SAR, and integrated peripherals in one PQFP package - enabling full-featured xDSL gateway design with minimal external logic and no FPGA co-processor.

Availability

IDT79RC32T351-100DH is available at Aetrix Electronics and suitable for xDSL residential gateways, SOHO routers, DSLAM line cards, and industrial protocol gateways requiring stable component supply across extended product lifecycles.

Supply support for IDT79RC32T351-100DH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT) is a fabless semiconductor company specializing in timing, memory interface, RF, and communications ICs for networking, computing, and consumer markets.

The IDT79RC32T351-100DH belongs to the Interprise™ family of integrated communications processors, designed specifically to consolidate ATM, Ethernet, USB, and serial interfaces into a single chip for cost-sensitive broadband access equipment.

FAQ

What is the maximum supported SDRAM capacity for the IDT79RC32T351-100DH?

The IDT79RC32T351-100DH supports up to 512 MB total SDRAM across two non-interleaved banks using its 26-bit address bus and 32-bit data path. It accommodates 4-bit, 8-bit, and 16-bit wide SDRAM chips and provides native SODIMM support, making it suitable for memory-constrained xDSL gateway designs requiring scalable packet buffering.

Does the IDT79RC32T351-100DH include an integrated USB transceiver?

Yes, the IDT79RC32T351-100DH integrates a full-speed USB 1.1 transceiver compliant with USB Revision 1.1 specifications. This eliminates the need for an external transceiver chip and supports control, interrupt, bulk, and isochronous endpoints at 12 Mb/s - enabling direct PC connectivity for firmware updates and diagnostics in consumer-grade devices using the IDT79RC32T351-100DH.

How does the ATM SAR functionality operate in the IDT79RC32T351-100DH?

The IDT79RC32T351-100DH implements a hybrid ATM SAR where hardware handles low-level tasks including CRC-32/AAL5 generation and checking, HEC calculation, 16-cell buffering, and short/long cell clipping. Software manages segmentation and reassembly logic, allowing flexible adaptation to different DSL standards. The UTOPIA Level 1 or Level 2 interface connects directly to xDSL chipsets without glue logic.

What are the key differences between Run-Time Mode and Real-Time Mode in the EJTAG interface of the IDT79RC32T351-100DH?

Run-Time Mode of the IDT79RC32T351-100DH EJTAG interface provides standard IEEE 1149.1 JTAG functionality for boundary scan and on-chip debugging. Real-Time Mode adds three dedicated PC trace status pins (EJTAG_PCST[2:0]) and EJTAG_DCLK to enable non-intrusive, cycle-accurate instruction tracing at the internal pipeline clock rate - essential for optimizing time-critical protocol stack performance in the IDT79RC32T351-100DH.

Can the IDT79RC32T351-100DH support both big-endian and little-endian operation?

Yes, the IDT79RC32T351-100DH's RC32300 CPU core supports runtime selection of big-endian or little-endian data ordering via a configuration bit in the status register. This flexibility allows the IDT79RC32T351-100DH to interface seamlessly with legacy big-endian networking protocols (e.g., TCP/IP byte order) and modern little-endian software stacks without hardware modification or performance penalty.