My Inquiry
My Account
Renesas IDT79RC32T355-150DH
- Part No.:
- IDT79RC32T355-150DH
- Manufacturer:
- Renesas
- Category:
- Microprocessors
- Package:
- 208-BFQFP
- Datasheet:
-
IDT79RC32T355-150DH.pdf
- Description:
- IC MPU INTERPRISE 150MHZ 208QFP
- Quantity:
- Payment:
- Shipping:
Inventory:2,877
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
IDT79RC32T355-150DH from Integrated Device Technology is a 32-bit integrated communications processor built around the RC32300 MIPS-II–enhanced CPU core, featuring 8KB instruction cache, 2KB data cache, MMU with 16-entry TLB, and on-chip SDRAM controller supporting up to 512 MB across two banks. It integrates dual 16550-compatible UARTs (up to 1.5 Mb/s), USB 1.1 device controller, 10/100 Ethernet MAC with MII, ATM SAR, TDM interface, I²C, three 32-bit timers, and 36 GPIO pins - deployed in xDSL residential gateways and SOHO routers.
For engineers reviewing the IDT79RC32T355-150DH datasheet, IDT79RC32T355-150DH pinout, IDT79RC32T355-150DH application, or IDT79RC32T355-150DH equivalent, key selection considerations include its 150 MHz pipeline frequency, 2.5V core / 3.3V I/O supply, 208-pin PQFP package, integrated ATM SAR with UTOPIA Level 1/2 support, and real-time debug via EJTAG with PC trace capability.
Technical Context
The IDT79RC32T355-150DH implements a hybrid ATM SAR architecture: hardware handles CRC-32/AAL5, HEC, cell buffering (16 cells), and UTOPIA timing, while software manages higher-layer segmentation/reassembly - enabling flexible xDSL chipset interfacing. Its memory subsystem uses a 26-bit address bus and 32-bit data bus with variable-width (8/16/32-bit) peripheral access, boot ROM support, and automatic SDRAM refresh.
The processor supports big/little-endian operation, per-line cache locking for deterministic DSP execution, and real-time debugging via dual-mode EJTAG (Run-Time Mode for standard JTAG, Real-Time Mode with PCST[2:0] pins for internal clock-synchronized trace). The DMA controller provides 16 channels with scatter/gather, unaligned, and burst transfer support across memory, peripherals, and on-chip interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Pipeline Frequency | 150 MHz - determines maximum instruction throughput and real-time response latency for telecom control tasks. |
| Core Voltage / I/O Voltage | 2.5 V core / 3.3 V I/O - requires dual-rail power design; enables compatibility with legacy 3.3V peripherals while reducing dynamic core power. |
| Cache | 8 KB 2-way instruction cache + 2 KB 2-way data cache - reduces external memory accesses for critical code/data, improving determinism in VoIP and modem firmware. |
| SDRAM Support | 2 banks, 32-bit data path, up to 512 MB total - enables cost-effective main memory for embedded Linux or RTOS-based gateway applications. |
| UART Speed | Up to 1.5 Mb/s - supports high-speed console logging, modem AT command channel, or serial management interfaces without external baud rate generators. |
| USB Interface | USB 1.1 full-speed (12 Mb/s) slave controller with integrated transceiver - eliminates need for external PHY in PC-connected consumer appliances. |
| Ethernet MAC | IEEE 802.3u-compliant 10/100 Mbps MAC with MII and auto-negotiation - allows direct connection to external PHYs for SOHO router LAN/WAN ports. |
Pinout & Package
Package: 208-pin Plastic Quad Flat Package (PQFP), 28 × 28 mm, 0.65 mm pitch, commercial temperature range (0°C to +70°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKP | System Clock Input | Master reference clock input; RC32300 pipeline frequency derived as integer multiple (×2/×3/×4) - must be stable low-jitter source for deterministic timing. |
| COLDRSTN | Cold Reset Input | Active-low asynchronous reset that initializes CPU state, loads boot configuration, and locks internal PLL - critical for reliable power-on sequence. |
| SYSCLKP | System Clock Output | Buffered/delayed version of CLKP; drives SDRAM clock inputs and RC32355's own SDCLKINP - ensures synchronous SDRAM read capture timing. |
| MADDR[25:0] | Memory Address Bus | 26-bit address bus for SDRAM, Flash, SRAM, and peripherals; upper bits [25:22] double as GPIOP[30:27] - enables flexible memory mapping and GPIO expansion. |
| MDATA[31:0] | Memory Data Bus | 32-bit bidirectional data path supporting 8/16/32-bit transfers; used for all memory and peripheral reads/writes - defines peak bandwidth to external devices. |
| GPIOP[0]–[35] | General Purpose I/O | 36 individually configurable pins; each supports input, output, or alternate function (e.g., UART, I²C, TDM, ATM) - replaces discrete logic for interface bridging and board-level customization. |
Key Features
| Feature | Design Value |
|---|---|
| RC32300 CPU Core | MIPS-II ISA with DSP instructions and cache locking - enables software-based 33.6/56 kbps modem emulation and real-time VoIP processing without dedicated ASICs. |
| Integrated ATM SAR | Hardware-accelerated CRC-32/AAL5, HEC, 16-cell buffering, and UTOPIA Level 1/2 support - offloads CPU from cell-level processing in xDSL line cards and DSLAM edge devices. |
| TDM Interface | Configurable 1–128 time slot support, Lucent CHI/GCI/Mitel ST-bus compatibility, up to 8.192 Mb/s - directly connects to telephone CODECs and audio A/D-D/A converters for voice-over-DSL. |
| EJTAG Debug Interface | Dual-mode (Run-Time + Real-Time) with PC trace pins (PCST[2:0]) - enables non-intrusive instruction tracing and cycle-accurate debugging for complex communications firmware. |
| Flexible Memory Controller | Supports SODIMM, Flash ROM, SRAM, dual-port RAM, and external wait-state generation - simplifies BOM by eliminating glue logic for mixed-memory systems. |
Applications
| xDSL Residential Gateway | SOHO Router |
|---|---|
|
Use Scenario: Aggregates POTS voice, Ethernet LAN, USB host, and ADSL line in single-box home gateway. IC Role / Device Role / Timing Role: Central system-on-chip executing routing, firewall, VoIP stack, ATM SAR, and TDM-to-Ethernet bridging. Use Value: Eliminates discrete CPU, ATM controller, TDM interface, and Ethernet MAC - reduces PCB area and bill-of-materials cost by >40% versus multi-chip solutions. |
Use Scenario: Provides wired LAN/WAN routing, QoS, and basic firewall for small office networks. IC Role / Device Role / Timing Role: Primary packet processor handling 10/100 Ethernet frame forwarding, NAT, and TCP/IP stack with integrated MACs. Use Value: On-chip dual UARTs enable console and out-of-band management; integrated SDRAM controller supports 32MB+ buffers for traffic shaping and deep packet inspection. |
| Cable Modem Termination System (CMTS) Edge Node | Voice-over-DSL Terminal Adapter |
|
Use Scenario: Processes DOCSIS upstream/downstream traffic at network edge with voice backhaul. IC Role / Device Role / Timing Role: Handles time-critical TDM voice framing, ATM cell assembly/disassembly, and Ethernet encapsulation. Use Value: Hardware TDM and ATM SAR reduce CPU load below 15% during full-rate voice+data traffic - enabling deterministic jitter <50 µs for VoIP. |
Use Scenario: Converts analog POTS lines to SIP/RTP packets over DSL infrastructure. IC Role / Device Role / Timing Role: Real-time DSP engine (via MIPS-II + cache locking) running echo cancellation, G.711/G.729 codecs, and TDM-CODEC interface. Use Value: Per-line cache locking guarantees sub-millisecond interrupt latency for voice sample capture - meeting ITU-T G.114 one-way delay requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integrated communications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT79RC32355-180DH | 180 MHz pipeline frequency; identical feature set and pinout - higher clock enables 20% greater packet processing throughput. | Preferred for high-concurrency SOHO routers with >100 concurrent VoIP sessions or multi-WAN failover. | Select when thermal headroom allows and sustained CPU utilization exceeds 75% at 150 MHz. |
| LSI RC32438-BG553 | ARM922T core (not MIPS); 200 MHz; integrated PCI interface; no native ATM SAR - requires external UTOPIA PHY and software SAR. | Better suited for Linux-based gateways requiring PCI expansion (e.g., WiFi add-on cards) but lacks hardware ATM acceleration. | Choose only if ARM toolchain familiarity, PCI connectivity, or longer product lifecycle outweighs loss of hardware ATM/TDM offload. |
Compared with IDT79RC32T355-150DH, the -180DH offers higher deterministic throughput for packet-intensive workloads without changing layout or firmware, while the RC32438 trades integrated telecom interfaces for general-purpose expandability - making it less suitable for xDSL-specific deployments requiring low-latency hardware SAR and TDM.
Availability
IDT79RC32T355-150DH is available at Aetrix Electronics and suitable for xDSL gateway development, SOHO router production, and voice-over-DSL terminal adapter manufacturing requiring stable component supply and long-term industrial availability.
Supply support for IDT79RC32T355-150DH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Integrated Device Technology (IDT) is a fabless semiconductor company specializing in timing, memory interface, RF, and high-performance communications ICs, acquired by Renesas Electronics in 2019.
The RC323xx family was designed as a unified platform for embedded communications infrastructure - integrating CPU, memory control, telecom interfaces (ATM, TDM, USB), and networking (Ethernet) to accelerate time-to-market for DSL, cable, and VoIP equipment.
FAQ
What is the maximum supported SDRAM capacity for IDT79RC32T355-150DH?
IDT79RC32T355-150DH supports up to 512 MB of SDRAM across two non-interleaved banks using its 26-bit address bus and 32-bit data path. It accommodates 4-bit, 8-bit, and 16-bit wide SDRAM chips and includes automatic refresh generation - enabling scalable memory configurations for Linux-based gateways or real-time VoIP stacks requiring large packet buffers.
Does IDT79RC32T355-150DH include an integrated USB transceiver?
Yes, IDT79RC32T355-150DH integrates a full-speed USB 1.1 transceiver compliant with USB Revision 1.1, supporting control, interrupt, bulk, and isochronous endpoints at 12 Mb/s. This eliminates the need for an external PHY in USB-connected consumer devices such as DSL modems with PC configuration interfaces.
Can IDT79RC32T355-150DH operate in both big-endian and little-endian modes?
Yes, IDT79RC32T355-150DH supports runtime selection of big-endian or little-endian data ordering via a configuration bit in the CPU status register. This flexibility allows porting of existing MIPS-based firmware (e.g., VxWorks or Linux) without architectural modification and simplifies interoperability with heterogeneous peripheral buses.
What debug capabilities does IDT79RC32T355-150DH provide?
IDT79RC32T355-150DH features Enhanced JTAG (EJTAG) with Run-Time Mode for standard boundary-scan and Real-Time Mode providing PC trace status pins (PCST[2:0]). This enables non-intrusive instruction-level tracing synchronized to the internal pipeline clock - essential for diagnosing timing-critical issues in VoIP call setup or ATM cell processing firmware.
Is IDT79RC32T355-150DH pin-compatible with other RC32355 speed grades?
Yes, IDT79RC32T355-150DH is pin-compatible with other RC32355 variants in the 208-pin PQFP package (e.g., IDT79RC32355-180DH), sharing identical pin functions, electrical characteristics, and thermal footprint. This allows frequency-scaling upgrades without PCB redesign - provided power delivery and cooling meet the higher-grade specifications.
IDT79RC32T355-150DH Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 208-BFQFP
- Series:
- Interprise™
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- MIPS-II
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 150MHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- SDRAM
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 1.1 (1)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 208-PQFP (28x28)
- Additional Interfaces:
- ATM, I2C, TDM, UART
IDT79RC32T355-150DH FAQ
1.How can I place an order for IDT79RC32T355-150DH through Aetrix?
Please submit a Request for Quotation (RFQ) for IDT79RC32T355-150DH on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for IDT79RC32T355-150DH reliable?
The price and inventory of IDT79RC32T355-150DH are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for IDT79RC32T355-150DH is usually 5 days.
3.What payment methods are accepted for IDT79RC32T355-150DH?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for IDT79RC32T355-150DH transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for IDT79RC32T355-150DH?
IDT79RC32T355-150DH orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your IDT79RC32T355-150DH order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for IDT79RC32T355-150DH?
For technical support, including IDT79RC32T355-150DH datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your IDT79RC32T355-150DH requirements.
6.How does Aetrix verify that IDT79RC32T355-150DH is sourced from the original manufacturer or authorized distributors?
All IDT79RC32T355-150DH products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that IDT79RC32T355-150DH meets industry standards.
7.What is the process for return or replacement of IDT79RC32T355-150DH?
All IDT79RC32T355-150DH units undergo pre-shipment inspection (PSI). If there is an issue with IDT79RC32T355-150DH, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The IDT79RC32T355-150DH part is unused and in its original packaging.
Return procedure for IDT79RC32T355-150DH:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
IDT79RC32T355-150DH Tags
-
AT91SAM9260B-CU-999
Microchip Technology
-
AT91SAM9G25-CU
Microchip Technology
-
ATSAMA5D27C-CU
Microchip Technology
-
AT91SAM9X35-CU
Microchip Technology
-
AT91SAM9X25-CU
Microchip Technology
-
MCIMX6Y2CVM08AB
NXP Semiconductors
.JPG)
-
AM3352BZCZ100
Texas Instruments
-
AT91SAM9260B-CU
Microchip Technology
-
AT91SAM9260B-QU
Microchip Technology
-
ATSAMA5D31A-CU
Microchip Technology
-
AT91SAM9G20B-CU-999
Microchip Technology
-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
