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Renesas IDT79RC32T355-150DHG
- Part No.:
- IDT79RC32T355-150DHG
- Manufacturer:
- Renesas
- Category:
- Microprocessors
- Package:
- 208-BFQFP
- Datasheet:
-
IDT79RC32T355-150DHG.pdf
- Description:
- IC MPU INTERPRISE 150MHZ 208QFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,556
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Product details
Overview
IDT79RC32T355-150DHG from Integrated Device Technology is a 32-bit integrated communications processor built around the RC32300 MIPS-II–enhanced CPU core, featuring 8KB instruction cache, 2KB data cache, MMU with 16-entry TLB, and on-chip SDRAM controller supporting 512 MB across two banks. It integrates dual 16550-compatible UARTs (up to 1.5 Mb/s), USB 1.1 device controller, 10/100 Ethernet MAC with MII, ATM SAR, TDM interface, I²C, three 32-bit timers, and 36 GPIO pins - deployed in xDSL residential gateways and SOHO routers.
For engineers reviewing the IDT79RC32T355-150DHG datasheet, IDT79RC32T355-150DHG pinout, IDT79RC32T355-150DHG application, or IDT79RC32T355-150DHG equivalent, key selection considerations include its 150 MHz pipeline frequency, 2.5V core / 3.3V I/O supply, 208-pin PQFP package, integrated EJTAG debug interface, and hardware-accelerated ATM SAR and TDM voice/data handling for VoIP-capable embedded systems.
Technical Context
The IDT79RC32T355-150DHG implements a hybrid ATM SAR architecture: hardware handles CRC-32/AAL5, HEC, cell buffering (16 cells), and UTOPIA level 1/2 interface timing, while software manages higher-layer segmentation and reassembly. Its TDM interface supports up to 128 time slots at 8.192 Mb/s with programmable frame generation and non-contiguous slot mapping for CODEC and audio A/D-D/A interfacing.
The processor's memory subsystem includes a 26-bit address bus, 32-bit variable-width data bus (8/16/32-bit), boot ROM support, six configurable banks (≤64 MB each), and SDRAM control with automatic refresh, page-mode optimization, and SODIMM compatibility - enabling high-bandwidth (380 MB/sec peak) external memory access with low-cost system implementation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Pipeline Frequency | 150 MHz - determines maximum instruction throughput and real-time response latency for routing, firewall, and modem emulation tasks. |
| Core Voltage / I/O Voltage | 2.5 V / 3.3 V - requires dual-rail power design; enables lower core power consumption while maintaining 3.3V peripheral interoperability. |
| Cache Configuration | 8 KB 2-way instruction cache + 2 KB 2-way data cache with per-line locking - ensures deterministic execution of DSP and protocol stacks without cache thrashing. |
| SDRAM Support | 2 banks, 512 MB total, 32-bit data path, 4/8/16-bit chip width - allows flexible, cost-optimized main memory architecture for embedded Linux or RTOS environments. |
| Integrated Peripherals | Dual UARTs (1.5 Mb/s), USB 1.1 device, 10/100 Ethernet MAC (MII), ATM SAR, TDM, I²C, 3×32-bit timers, 36 GPIO - eliminates need for discrete interface ICs in broadband CPE designs. |
| Debug Interface | EJTAG with Run-Time and Real-Time modes - provides standard JTAG boundary scan plus PC trace status pins (PCST[2:0]) for cycle-accurate software profiling. |
| Package | 208-pin PQFP (DHG suffix) - surface-mount compatible with standard reflow profiles; thermal performance validated for 0°C to +70°C commercial operation. |
Pinout & Package
Package: 208-pin Plastic Quad Flat Package (PQFP), body size 28 × 28 mm, 0.65 mm pitch, RoHS-compliant lead finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKP | System Clock Input | Master reference clock input; RC32300 pipeline frequency derived as integer multiple (×2/×3/×4) - critical for synchronous timing across all internal blocks. |
| COLDRSTN | Cold Reset Input | Active-low asynchronous reset initiating full initialization: boot config load, PLL lock, and state machine reset - required for power-on and recovery sequences. |
| SYSCLKP | System Clock Output | Buffered/delayed copy of CLKP; drives external SDRAM clocks and feeds SDCLKINP - ensures synchronous read capture timing for SDRAM interface. |
| MADDR[25:0] | Memory Address Bus | 26-bit address bus for SDRAM, Flash, SRAM, and peripheral access; upper bits (MADDR[22:25]) double as GPIOP[27:30] - enables memory-mapped I/O flexibility. |
| MDATA[31:0] | Memory Data Bus | 32-bit bidirectional data path supporting 8/16/32-bit transfers; used by SDRAM, peripheral devices, and boot ROM - defines peak bandwidth capability (380 MB/sec). |
| GPIOP[0–35] | Configurable I/O Bank | 36 individually programmable pins supporting input/output/alternate functions (UART, I²C, TDM, ATM, USB, DMA, EJTAG); default reset state is GPIO - enables hardware reuse and board-level signal routing optimization. |
Key Features
| Feature | Design Value |
|---|---|
| RC32300 CPU Core | MIPS-II ISA with DSP instructions and cache locking - enables software-based 33.6/56 kbps modem emulation and real-time VoIP processing without external DSP. |
| Integrated ATM SAR | Hardware CRC-32/AAL5, HEC, 16-cell buffering, UTOPIA L1/L2 support - offloads CPU from cell-level processing in xDSL modems and Layer 3 switches. |
| TDM Voice Interface | 1–128 time slot support, 8.192 Mb/s max rate, Lucent CHI/GCI/Mitel ST-bus compatibility - directly interfaces telephone CODECs and audio converters for VoIP gateway voice channels. |
| Flexible Memory Controller | 6 banks (≤64 MB each), SODIMM support, automatic SDRAM refresh, Intel/Motorola wait-state modes - simplifies BOM and PCB layout for cost-sensitive residential CPE. |
| EJTAG Debug Architecture | Run-Time (standard JTAG) + Real-Time (PCST[2:0] trace pins) modes - enables both functional validation and cycle-accurate firmware optimization in production development. |
Applications
| xDSL Residential Gateway | SOHO Router with VoIP |
|---|---|
|
Use Scenario: Aggregates POTS voice, Ethernet LAN, and ADSL line into single residential CPE unit with firewall and QoS. IC Role / Device Role / Timing Role: System-on-chip host processor executing routing stack, ATM SAR, TDM voice channelization, and USB/Ethernet bridging. Use Value: Eliminates discrete PHY, SAR, CODEC, and memory controller ICs - reduces bill-of-materials and board area by >40% versus multi-chip solutions. |
Use Scenario: Small office/home office router supporting simultaneous data forwarding, SIP-based VoIP call handling, and PC connectivity via USB/Ethernet. IC Role / Device Role / Timing Role: Central communications processor managing packet routing, voice codec offload via TDM, and USB device enumeration for configuration. Use Value: On-chip 10/100 Ethernet MAC and USB 1.1 controller enable direct PC connection without external transceivers - accelerates time-to-market for certified VoIP gateways. |
| Cable Modem Termination System (CMTS) Edge Node | Industrial Protocol Gateway |
|
Use Scenario: Edge node aggregating DOCSIS upstream/downstream traffic with legacy TDM voice backhaul over IP. IC Role / Device Role / Timing Role: Communications processor performing DOCSIS MAC layer processing, TDM-to-IP encapsulation, and ATM cell relay. Use Value: Integrated TDM and ATM SAR allow direct interfacing to legacy telephony infrastructure while supporting modern IP transport - extends equipment lifecycle without redesign. |
Use Scenario: Field-deployable gateway translating industrial protocols (e.g., Modbus TCP ↔ PROFIBUS) in factory automation networks. IC Role / Device Role / Timing Role: Embedded host running protocol stacks, managing dual Ethernet ports, and interfacing to fieldbus peripherals via GPIO and UARTs. Use Value: 36 GPIO pins with interrupt/NMI capability and dual high-speed UARTs support custom peripheral bridging - avoids FPGA or CPLD co-processor requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integrated communications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT79RC32355-180DHG | 180 MHz pipeline frequency; identical feature set and pinout - higher clock enables increased packet-per-second throughput in routing-intensive deployments. | Preferred for high-concurrency SOHO routers requiring >100 Mbps sustained forwarding under QoS and firewall load. | Select when thermal headroom permits and application demands higher deterministic instruction throughput without changing PCB layout. |
| AMD Alchemy Au1550 | MIPS32 core, 333 MHz max, integrated DDR SDRAM controller, no native ATM SAR or TDM - relies on software SAR and external CODEC interface. | Better suited for Linux-based media gateways where software flexibility outweighs hardware acceleration for voice/data convergence. | Choose when migrating to newer Linux BSPs and requiring DDR memory support, but accept added firmware complexity for ATM/TDM functions. |
Compared with IDT79RC32T355-150DHG, the -180DHG offers higher deterministic throughput for packet forwarding, while the Au1550 trades hardware acceleration for broader OS support and DDR scalability - making the IDT79RC32T355-150DHG optimal for cost-sensitive, fixed-function xDSL/VoIP CPE with strict real-time latency requirements.
Availability
IDT79RC32T355-150DHG is available at Aetrix Electronics and suitable for xDSL gateways, SOHO routers, VoIP edge nodes, and industrial protocol gateways requiring stable component supply, long-lifecycle assurance, and traceable sourcing for production programs.
Supply support for IDT79RC32T355-150DHG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Integrated Device Technology (IDT) is a fabless semiconductor company specializing in timing, memory interface, RF, and communications ICs - acquired by Renesas Electronics in 2019.
IDT79RC32T355-150DHG belongs to the Interprise™ family of integrated communications processors, designed specifically for cost-optimized, high-integration broadband customer premises equipment requiring hardware-accelerated ATM, TDM, and Ethernet functionality.
FAQ
What is the maximum supported SDRAM capacity for IDT79RC32T355-150DHG?
IDT79RC32T355-150DHG supports up to 512 MB of SDRAM across two non-interleaved banks, using a 32-bit data path and configurable 4-bit, 8-bit, or 16-bit wide SDRAM chips. This capacity is sufficient for running embedded Linux or real-time operating systems with multiple concurrent network services in xDSL and VoIP applications. The SDRAM controller also supports SODIMM modules and automatic refresh generation.
Does IDT79RC32T355-150DHG include an integrated USB transceiver?
Yes, IDT79RC32T355-150DHG integrates a full-speed USB 1.1 transceiver compliant with USB Revision 1.1, supporting control, interrupt, bulk, and isochronous endpoints at 12 Mb/s. The USBDP and USBDN pins provide differential signaling directly to the USB connector, eliminating the need for an external transceiver in USB device mode - commonly used for PC-based configuration and firmware updates.
Can IDT79RC32T355-150DHG operate in both big-endian and little-endian modes?
Yes, IDT79RC32T355-150DHG supports both big-endian and little-endian data ordering through a configuration bit in the CPU status register. This flexibility allows the IDT79RC32T355-150DHG to interface seamlessly with legacy big-endian peripherals (e.g., certain telecom ASICs) or modern little-endian software stacks (e.g., Linux, VxWorks), simplifying integration across heterogeneous system architectures.
What is the role of the EJTAG interface in IDT79RC32T355-150DHG debugging?
IDT79RC32T355-150DHG implements Enhanced JTAG (EJTAG) with two operational modes: Run-Time Mode provides standard IEEE 1149.1 boundary scan for basic debug and programming, while Real-Time Mode adds PCST[2:0] trace pins for cycle-accurate instruction flow visibility. This dual-mode capability enables both functional validation and deep firmware optimization during development of routing, firewall, or VoIP applications on the IDT79RC32T355-150DHG.
How does the ATM SAR function in IDT79RC32T355-150DHG differ from a fully hardware-based SAR?
IDT79RC32T355-150DHG implements a hybrid ATM SAR: hardware handles low-level tasks including CRC-32/AAL5 generation, HEC checking, 16-cell buffering, and UTOPIA timing, while software manages segmentation, reassembly, and higher-layer protocol logic. This architecture reduces silicon area and power versus full hardware SAR, yet maintains real-time performance for xDSL modem applications - distinguishing IDT79RC32T355-150DHG from purely software-only or fully dedicated SAR solutions.
IDT79RC32T355-150DHG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 208-BFQFP
- Series:
- Interprise™
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- MIPS-II
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 150MHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- SDRAM
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 1.1 (1)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 208-PQFP (28x28)
- Additional Interfaces:
- ATM, I2C, TDM, UART
IDT79RC32T355-150DHG FAQ
1.How can I place an order for IDT79RC32T355-150DHG through Aetrix?
Please submit a Request for Quotation (RFQ) for IDT79RC32T355-150DHG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for IDT79RC32T355-150DHG reliable?
The price and inventory of IDT79RC32T355-150DHG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for IDT79RC32T355-150DHG is usually 5 days.
3.What payment methods are accepted for IDT79RC32T355-150DHG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for IDT79RC32T355-150DHG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for IDT79RC32T355-150DHG?
IDT79RC32T355-150DHG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your IDT79RC32T355-150DHG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for IDT79RC32T355-150DHG?
For technical support, including IDT79RC32T355-150DHG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your IDT79RC32T355-150DHG requirements.
6.How does Aetrix verify that IDT79RC32T355-150DHG is sourced from the original manufacturer or authorized distributors?
All IDT79RC32T355-150DHG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that IDT79RC32T355-150DHG meets industry standards.
7.What is the process for return or replacement of IDT79RC32T355-150DHG?
All IDT79RC32T355-150DHG units undergo pre-shipment inspection (PSI). If there is an issue with IDT79RC32T355-150DHG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The IDT79RC32T355-150DHG part is unused and in its original packaging.
Return procedure for IDT79RC32T355-150DHG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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