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Renesas IDT79RC32V332-133DHI
- Part No.:
- IDT79RC32V332-133DHI
- Manufacturer:
- Renesas
- Category:
- Microprocessors
- Package:
- 208-BFQFP
- Datasheet:
-
IDT79RC32V332-133DHI.pdf
- Description:
- IC MPU INTERPRISE 133MHZ 208QFP
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
IDT79RC32V332-133DHI from Integrated Device Technology is a 32-bit integrated communications processor featuring an RISCore 32300 CPU core compliant with Enhanced MIPS-II ISA, operating at up to 133 MHz, with 8KB instruction cache and 2KB data cache, and integrated SDRAM controller supporting up to 512MB - deployed in telecom access equipment and industrial gateways requiring deterministic real-time I/O and PCI-based peripheral expansion.
For engineers reviewing the IDT79RC32V332-133DHI datasheet, IDT79RC32V332-133DHI pinout, IDT79RC32V332-133DHI application, or IDT79RC32V332-133DHI equivalent, key selection considerations include its 208-pin QFP package, 3.3V core/I/O supply with 5V-tolerant I/O, PCI 2.2 compliance, EJTAG debug interface, and dual-mode boot configuration via mem_addr[21:20].
Technical Context
The IDT79RC32V332-133DHI implements a scalar 5-stage pipeline RISCore 32300 CPU core with MMU (32-page TLB), cache locking per line, and big/little-endian support. Its local bus operates up to 75 MHz with 23-bit address/32-bit data width, while the integrated SDRAM controller manages four banks at up to 75 MHz with automatic refresh and support for 16–512Mb devices.
The device integrates a full 32-bit PCI 2.2 bridge (50 MHz), four 32-bit timers, 16550-compatible UART (up to 1.5 Mb/s), SPI master interface, and a 4-channel DMA controller with scatter/gather, unaligned transfer, and byte-lane alignment - all coordinated through a centralized interrupt controller and programmable I/O module.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RISCore 32300, Enhanced MIPS-II ISA, 133 MHz max operation - enables execution of existing MIPS binaries and kernel compatibility with modern embedded OSes. |
| Cache | 8KB 2-way set associative instruction cache + 2KB 2-way set associative data cache with line locking - reduces memory latency for real-time tasks like VoIP packet processing. |
| SDRAM Support | 4-bank controller, up to 512MB total, 16–512Mb device depths, automatic refresh - allows use of commodity SODIMM/DIMM modules without external logic. |
| PCI Interface | 32-bit, 50 MHz, Revision 2.2 compliant, host/satellite mode, serial EEPROM config loading - enables plug-and-play integration of PC-standard peripherals in embedded systems. |
| Local Bus | 23-bit address, 32-bit data, 75 MHz max, 6 chip-selects (8MB/bank), 8-/16-/32-bit timing flexibility - supports mixed-width legacy memories (Flash, SRAM, dual-port) and boot PROM. |
| Debug | EJTAG interface (IEEE 1149.1), boundary scan, CPU/DMA transaction differentiation signals - enables low-cost in-circuit emulation and logic analyzer-assisted system bring-up. |
| Package & Temp | 208-pin QFP, commercial grade (0°C to +70°C), 3.3V core/I/O with 5V-tolerant I/O pins - simplifies power design and ensures compatibility with standard PCB assembly processes. |
Pinout & Package
208-pin Plastic Quad Flat Pack (QFP), 28 × 28 mm body, 0.5 mm pitch, lead-free compatible. Thermal performance rated for <2.0 W peak power dissipation under full load.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| mem_data[31:0] | Local system bidirectional data bus | Primary 32-bit path for memory, I/O, and SDRAM transfers; tri-state during idle cycles to reduce bus contention. |
| mem_addr[22:2] | Memory/SDRAM address bus | 21-bit address lines shared between local memory and SDRAM; upper bits (22:17) multiplexed with boot mode configuration. |
| pci_ad[31:0] | PCI multiplexed address/data bus | Carries address in first cycle, then data in subsequent cycles; requires external latching for reliable capture in satellite mode. |
| sdram_cs_n[3:0] | SDRAM bank chip select | Four independent active-low enables for discrete or modular SDRAM banks; supports non-interleaved 4-bank topology. |
| cpu_masterclk | CPU system clock input | Single-ended clock input driving internal PLL; frequency determines CPU core speed and local bus timing base. |
| jtag_tck / ejtag_dclk | JTAG/EJTAG clock | Dual-function clock pin: JTAG test clock (independent of system clock) and EJTAG debug clock (derived from CPU pipeline). |
Key Features
| Feature | Design Value |
|---|---|
| Enhanced MIPS-II ISA extensions | Includes count-leading-zeros/ones, conditional move, DSP instructions - accelerates VoIP compression, modem emulation, and routing table lookups. |
| Programmable cache write policies | Per-page selection of write-through/no-write-allocate, write-through/write-allocate, or write-back - enables precise control over memory coherency in multi-master systems. |
| Flexible local bus timing | Automatic wait-state generation and programmable setup/hold for 8-/16-/32-bit peripherals - eliminates need for external glue logic when interfacing legacy Flash or dual-port RAM. |
| PCI 2.2 bridge with satellite mode | Enables RC32332 to act as PCI target or initiator; satellite mode supports warm reset and EEPROM-based configuration loading - simplifies add-in card designs. |
| Integrated 16550 UART + SPI master | UART supports 1.5 Mb/s baud with FIFO; SPI drives EEPROM, ADC, or configuration PROMs - provides dual-path firmware update and sensor interface capability. |
Applications
| DSL Access Multiplexer | Industrial Protocol Gateway |
|---|---|
Use Scenario: Aggregates multiple ADSL lines into a single Ethernet uplink using ATM segmentation/reassembly and QoS scheduling. IC Role / Device Role / Timing Role: Primary system controller executing Linux-based protocol stack, managing SDRAM for packet buffering, and driving PCI-connected PHYs and switch controllers. Use Value: 133 MHz CPU throughput and integrated DMA enable line-rate packet forwarding with <5 µs interrupt latency for real-time traffic shaping. | Use Scenario: Bridges Modbus RTU over RS-485 to EtherNet/IP via embedded gateway firmware, with secure firmware updates via UART. IC Role / Device Role / Timing Role: Real-time deterministic controller running FreeRTOS, using PIO pins for isolated digital I/O, and SDRAM for protocol translation buffers. Use Value: Cache locking and MMU support allow guaranteed response to fieldbus interrupts within 20 µs, meeting IEC 61131-3 cycle time requirements. |
| PCI-Based Test Instrument Card | Legacy System Emulation Module |
Use Scenario: PCIe-to-PCI bridge card hosting custom analog acquisition FPGA, with host CPU offloading signal processing to RC32332. IC Role / Device Role / Timing Role: PCI target managing local SDRAM as DMA buffer, coordinating with host via mailbox registers, and controlling FPGA via SPI. Use Value: 4-channel scatter/gather DMA and PCI 2.2 compliance enable sustained 120 MB/s data streaming from FPGA to host memory without CPU intervention. | Use Scenario: Replaces obsolete 68040-based controller in medical imaging chassis, emulating legacy bus timing and interrupt vectors. IC Role / Device Role / Timing Role: Pin-compatible system-on-chip replacement executing original firmware binary, using local bus to drive same peripheral ASICs and memory map. Use Value: MIPS-II binary compatibility and programmable local bus timing protocols allow drop-in replacement without PCB redesign or firmware recompilation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integrated communications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT79RC32V332-150DHI | 150 MHz CPU speed grade; identical pinout, package, and feature set - higher clock margin for compute-intensive routing stacks. | Same SDRAM/PCI/local bus architecture; requires validated power delivery for 150 MHz operation. | Select when >133 MHz headroom needed for future firmware upgrades or higher packet-per-second throughput. |
| IDT79RC32V252-133DHI | 2.5V core supply (vs. 3.3V); otherwise identical functionality, pinout, and timing - lower dynamic power and thermal footprint. | Requires separate 2.5V rail; I/O remains 3.3V, preserving peripheral compatibility. | Select for thermally constrained designs where <1.5 W peak power is mandatory, e.g., fanless DIN-rail enclosures. |
Compared with IDT79RC32V332-133DHI, the -150DHI variant delivers 13% higher CPU throughput for latency-sensitive packet processing, while the -252DHI reduces core power by ~35% at same frequency - both retain full software and hardware compatibility but impose distinct power delivery and thermal management requirements.
Availability
IDT79RC32V332-133DHI is available at Aetrix Electronics and suitable for DSL aggregation platforms, industrial protocol gateways, PCI test instrumentation, and legacy system emulation requiring stable component supply across extended product lifecycles.
Supply support for IDT79RC32V332-133DHI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Integrated Device Technology (IDT) is a fabless semiconductor company specializing in timing, memory interface, RF, and high-performance embedded processors - acquired by Renesas Electronics in 2019.
The IDT Interprise™ family, including IDT79RC32V332-133DHI, was designed to deliver cost-optimized, highly integrated communications processors for carrier-grade access equipment and industrial edge systems requiring PCI expansion and real-time determinism.
FAQ
What is the maximum SDRAM capacity supported by the IDT79RC32V332-133DHI?
The IDT79RC32V332-133DHI supports up to 512MB of SDRAM across four banks, accommodating device densities from 16Mb to 512Mb per chip. It directly controls discrete SDRAM chips, SODIMMs, or DIMMs with automatic refresh generation and on-chip page comparators to minimize access latency. This capacity is confirmed in the May 2004 datasheet revision under the Synchronous-DRAM Interface section.
Does the IDT79RC32V332-133DHI support both big-endian and little-endian operation?
Yes, the IDT79RC32V332-133DHI supports both big-endian and little-endian operation at the CPU core level and extends this flexibility to the local bus interface and peripheral controllers. The endian mode is configurable per subsystem via dedicated control registers, enabling interoperability with heterogeneous peripheral buses and legacy firmware binaries - a feature explicitly documented in the CPU Execution Core and Local Bus Interface sections of the datasheet.
Can the IDT79RC32V332-133DHI operate as a PCI bus master and target simultaneously?
No, the IDT79RC32V332-133DHI operates in either PCI host mode (acting as bus master) or satellite mode (acting as bus target), not both simultaneously. In host mode, it initiates transactions and grants access to external devices; in satellite mode, it responds to configuration reads/writes and can perform warm resets. Mode selection is determined at reset via mem_addr[20], as specified in the Pin Description Table and PCI Bus Bridge section.
What debug interfaces are available on the IDT79RC32V332-133DHI?
The IDT79RC32V332-133DHI provides IEEE 1149.1-compliant JTAG for boundary-scan testing and EJTAG for in-circuit emulation. EJTAG adds real-time program counter tracing (ejtag_tpc), debug exception triggering (ejtag_debugboot), and CPU/DMA transaction differentiation signals (debug_cpu_dma_n). These interfaces are electrically and functionally distinct but share physical pins jtag_tck, jtag_tdi/ejtag_dint_n, and jtag_tdo/ejtag_tpc - details confirmed in the Debug Support and JTAG Interface Signals sections.
Is the IDT79RC32V332-133DHI pin-compatible with other members of the RC32332 family?
Yes, the IDT79RC32V332-133DHI is fully pin-compatible with all speed grades (-100, -133, -150) and voltage variants (-332 for 3.3V core, -252 for 2.5V core) within the RC32332 family, sharing the identical 208-pin QFP package and pin assignment. Differences are limited to AC timing parameters and power supply requirements - verified in the Packaging and Revision History sections of the datasheet, which state "Changed to DH package" and confirm consistent pin descriptions across revisions.
IDT79RC32V332-133DHI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 208-BFQFP
- Series:
- Interprise™
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- MIPS-II
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 133MHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- SDRAM
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- -
- SATA:
- -
- USB:
- -
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 208-PQFP (28x28)
- Additional Interfaces:
- PCI, SPI, UART
IDT79RC32V332-133DHI FAQ
1.How can I place an order for IDT79RC32V332-133DHI through Aetrix?
Please submit a Request for Quotation (RFQ) for IDT79RC32V332-133DHI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for IDT79RC32V332-133DHI reliable?
The price and inventory of IDT79RC32V332-133DHI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for IDT79RC32V332-133DHI is usually 5 days.
3.What payment methods are accepted for IDT79RC32V332-133DHI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for IDT79RC32V332-133DHI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for IDT79RC32V332-133DHI?
IDT79RC32V332-133DHI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your IDT79RC32V332-133DHI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for IDT79RC32V332-133DHI?
For technical support, including IDT79RC32V332-133DHI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your IDT79RC32V332-133DHI requirements.
6.How does Aetrix verify that IDT79RC32V332-133DHI is sourced from the original manufacturer or authorized distributors?
All IDT79RC32V332-133DHI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that IDT79RC32V332-133DHI meets industry standards.
7.What is the process for return or replacement of IDT79RC32V332-133DHI?
All IDT79RC32V332-133DHI units undergo pre-shipment inspection (PSI). If there is an issue with IDT79RC32V332-133DHI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The IDT79RC32V332-133DHI part is unused and in its original packaging.
Return procedure for IDT79RC32V332-133DHI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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