Infineon Technologies IR1150STRPBF

Overview

IR1150STRPBF from Infineon Technologies is a continuous conduction mode (CCM) boost-type power factor correction (PFC) control IC implementing proprietary One Cycle Control (OCC), operating at programmable 50–200 kHz switching frequency, featuring cycle-by-cycle peak current limiting, programmable output overvoltage protection (104–107% VREF), and micropower sleep mode (<200 µA). It enables EN61000-3-2 Class D-compliant PFC in AC-DC front-end supplies for LED drivers, PC power supplies, and industrial SMPS.

For engineers reviewing the IR1150STRPBF datasheet, IR1150STRPBF pinout, IR1150STRPBF application, or IR1150STRPBF equivalent, key selection considerations include its OCC-based line-voltage-sensorless operation, 93–98% max duty cycle, 1.5 A peak gate drive, internal 7.0 V reference (±0.1 V), and dual-loop (voltage + current) control architecture optimized for THD reduction and light-load efficiency.

Technical Context

The IR1150STRPBF implements a two-loop control system: an inner current loop using embedded input voltage dependency to shape average input current without external line sensing, and an outer voltage loop regulating DC bus via transconductance error amplifier (gm = 40 µS) with programmable soft start. The OCC technique eliminates traditional multiplier-based analog computation, reducing component count and noise sensitivity.

Its gate driver delivers ±1.5 A peak current with 20–70 ns rise/fall times (C_LOAD = 1–10 nF), internally clamped to 13 V, and integrates blanking time (230–450 ns) for ISNS noise immunity. Protection includes brownout (V_CC UVLO = 10.7 V), open-loop (V_FB threshold = 19% V_REF), and OVP latching with 450 mV hysteresis.

Key Specifications

Pinout & Package

IR1150STRPBF is housed in an 8-pin SOIC package (body width 3.9 mm, lead pitch 1.27 mm), RoHS-compliant and halogen-free per PbF designation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PFC controller applications.

Compared with UCC28070DR and FAN6982MY, IR1150STRPBF uniquely combines OCC-based line-sensorless CCM operation, programmable frequency, and micropower sleep mode-enabling compact, low-cost, and regulatory-compliant PFC in 150–400 W universal-input systems without design compromises.

Availability

IR1150STRPBF is available at Aetrix Electronics and suitable for LED driver front-ends, PC ATX power supplies, and industrial AC-DC adapters requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for IR1150STRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive, and industrial control ICs, with global manufacturing and quality certifications including ISO 9001 and IATF 16949.

The IR1150STRPBF belongs to Infineon's µPFC product line, designed specifically for cost-effective, high-efficiency CCM boost PFC in universal-input AC-DC converters targeting energy-efficient lighting, computing, and industrial power systems.

FAQ

What is the minimum external resistor value for the FREQ pin to achieve 200 kHz operation?

The IR1150STRPBF requires a 37 kΩ resistor from FREQ to COM to set 200 kHz switching frequency, as confirmed by the datasheet's oscillator section (R_SET ≈ 165 kΩ – 37 kΩ range). Using a lower resistance risks exceeding the absolute maximum FREQ pin voltage (10.5 V) and may cause frequency instability or damage under high V_CC conditions.

How does the IR1150STRPBF implement line-voltage-sensorless current shaping?

It uses One Cycle Control (OCC) to embed line voltage dependency into the current loop via the relationship between duty cycle and instantaneous input voltage. The inner current loop compares sensed inductor current (via ISNS) against a dynamically scaled ramp derived from V_COMP, eliminating need for separate line voltage sensing circuitry while maintaining sinusoidal input current.

Can the OVP/EN pin be used simultaneously for overvoltage protection and sleep mode activation?

No - the OVP/EN pin serves both functions but not concurrently. When used for OVP, it monitors DC bus via resistive divider and latches off GATE above 105.5% V_REF. To activate sleep mode, the pin must be actively pulled below 0.62 V (typ), which overrides OVP function and forces micropower state; external logic is required for dynamic mode switching.

What is the recommended layout practice for the ISNS pin to ensure noise immunity?

Place a 100 Ω resistor in series with the ISNS trace near the IC, followed by a 1 nF capacitor to COM, forming an RC filter before the pin. Route the ISNS trace away from high-dV/dt nodes (e.g., MOSFET drain, boost diode cathode), use ground guard ring around the sense path, and keep trace length under 5 mm to minimize pickup of switching noise.