Infineon Technologies IR3621F

Overview

IR3621F from Infineon Technologies is a dual-phase synchronous buck PWM controller with integrated high- and low-side drivers, supporting both independent dual-output and current-sharing single-output configurations. It operates at up to 500 kHz per phase, features two independent soft-starts, pre-bias startup, and programmable hiccup/latched overcurrent protection. Used in graphics card VRMs and DDR memory power supplies.

For engineers reviewing the IR3621F datasheet, IR3621F pinout, IR3621F application, or IR3621F equivalent, key selection considerations include its 28-pin TSSOP package, 0.8 V reference accuracy, dual-phase DCR-based current sharing, VcH1/VcH2 supply range (10–20 V), and thermal shutdown at 125 °C junction temperature.

Technical Context

The IR3621F implements voltage-mode control with two independent error amplifiers and ramp generators, enabling precise regulation of either two separate outputs or coordinated current sharing via inductor DCR sensing. Its 180° out-of-phase operation reduces input/output ripple and capacitor stress.

It integrates a 6.2 V internal LDO (VOUT3), supports external frequency synchronization, and uses dedicated OCSet pins for MOSFET R_DS(on)-based current limiting. The Hiccup pin selects between hiccup-mode or latched shutdown on overcurrent events.

Key Specifications

Pinout & Package

The IR3621F is housed in a 28-pin TSSOP package with exposed pad (RoHS-compliant, PbF version available). Pin 1 is PGood; pins 2–4 are Vcc, VOUT3, and Rt; pins 5–6 are VSEN2/VSEN1; pins 7–8 are Fb2/Fb1; pins 9–10 are Comp2/Comp1; pins 11–12 are SS2/SD and SS1/SD; pins 13–14 are OCSet2/OCSet1; pins 15–16 are VcH2/VcH1; pins 17–18 are HDrv2/HDrv1; pins 19–20 are PGnd2/PGnd1; pins 21–22 are LDrv2/LDrv1; pin 23 is VCL; pin 24 is Sync; pin 25 is Hiccup; pin 26 is VP2; pin 27 is VREF; pin 28 is Gnd.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-phase synchronous buck controller applications.

Compared with MP2940A and ISL6322IRZ, the IR3621F offers unique value in fixed-function, analog-controlled dual-phase designs where TSSOP packaging, pre-bias startup, and lossless DCR current sharing are prioritized over digital configurability or integrated FETs.

Availability

IR3621F is available at Aetrix Electronics and suitable for graphics card VRMs, DDR memory power supplies, and telecom point-of-load converters requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.

Supply support for IR3621F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power management, automotive, and industrial control ICs, with global manufacturing and quality certification to ISO 9001 and IATF 16949.

The IR3621F belongs to Infineon's IR36xx family of analog multi-phase controllers, designed specifically for high-efficiency, cost-sensitive DC-DC conversion in graphics, memory, and embedded networking applications.

FAQ

What is the function of the VP2 pin on the IR3621F?

The VP2 pin is the non-inverting input to the second error amplifier. In current-share mode, it connects to the programming resistor to establish current balance; in dual-output mode, it ties to VREF when Fb2 serves as the feedback node. Its voltage range is specified as 0.25–0.95×VREF, and it sources/sinks ≤3 µA-ensuring minimal loading on external divider networks.

Can the IR3621F operate without an external oscillator resistor (Rt)?

No. The Rt pin (Pin 4) requires an external resistor to ground to set the oscillator frequency. With no resistor, the internal oscillator defaults to an undefined state and the device will not generate valid PWM signals. Typical values range from 15 kΩ (500 kHz) to 30.9 kΩ (300 kHz), per the datasheet's Rt vs. Freq curve.

How does pre-bias startup work on the IR3621F?

Pre-bias startup prevents reverse current flow when the output is already charged before enable. The controller monitors VSEN1/VSEN2 during startup; if voltage exceeds 0.1×VREF, it inhibits gate drive until the soft-start ramp reaches the feedback level-avoiding discharge through low-side FETs and protecting downstream loads like DDR termination networks.

Is the IR3621F pin-compatible with the IR3621M (MLPQ package)?

No. The IR3621F uses a 28-pin TSSOP package with different pin mapping and thermal characteristics (θ_JA = 36.0 °C/W), while the IR3621M uses a 32-pin MLPQ 5×5 mm package (θ_JA = 75.5 °C/W). Pin functions overlap partially, but physical layout, grounding scheme, and driver decoupling requirements differ significantly-requiring separate PCB designs.