Renesas IS82C59AZX96

Overview

IS82C59AZX96 from Intersil is a CMOS Priority Interrupt Controller designed to offload interrupt management from microprocessors such as 80C86/88, 80C286, and 8080/85. It handles up to eight vectored priority interrupt sources, supports cascading to 64 levels, operates at 12.5MHz max, consumes ≤1mA/MHz in active mode, and uses a single +5V supply. It serves as the central interrupt arbiter in legacy x86 and MCS-80/85 embedded control systems.

For engineers reviewing the IS82C59AZX96 datasheet, IS82C59AZX96 pinout, IS82C59AZX96 application, or IS82C59AZX96 equivalent, key selection criteria include its 28-pin PLCC Pb-free package, TTL-compatible I/O, static CMOS design enabling zero wait-state operation with 80C286 at 12.5MHz, edge- or level-triggered IR inputs, and dual-mode (8080/85 vs. 80C86/88) vectoring support.

Technical Context

The IS82C59AZX96 implements a fully static CMOS architecture with three internal registers - Interrupt Request Register (IRR), In-Service Register (ISR), and Interrupt Mask Register (IMR) - coordinated by priority resolver logic. Its read/write control logic accepts Initialization Command Words (ICW1–ICW4) and Operation Command Words (OCW1–OCW3) to configure nested/rotating priority, special mask, and polled modes.

It features dedicated cascade lines (CAS0–CAS2) for master/slave configuration, a dual-function SP/EN pin for buffered mode enable or slave programming, and INTA-synchronized vector output supporting both CALL opcode delivery (8080/85) and direct vector byte transfer (80C86/88/286). Internal pull-up resistors on IR0–IR7 eliminate external biasing.

Key Specifications

Pinout & Package

IS82C59AZX96 is housed in a 28-lead Plastic Leaded Chip Carrier (PLCC) package with J-lead geometry, Pb-free matte tin terminations, and JEDEC-standard footprint N28.45. It is designed for reflow soldering and compatible with automated SMT placement.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar priority interrupt controller applications.

Compared with IS82C59A and CS82C59AZ96, IS82C59AZX96 uniquely combines industrial temperature range, Pb-free PLCC packaging, and tape-and-reel delivery-making it the only option qualified for volume-manufactured, thermally demanding embedded systems requiring long-term supply continuity.

Availability

IS82C59AZX96 is available at Aetrix Electronics and suitable for industrial PLC backplanes, legacy x86 embedded controllers, and military avionics subsystems requiring stable component supply across extended product lifecycles.

Supply support for IS82C59AZX96 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Intersil Corporation was a U.S.-based semiconductor company specializing in high-performance analog and mixed-signal ICs, later acquired by Renesas Electronics in 2017.

The 82C59A family was developed as a CMOS drop-in replacement for the industry-standard NMOS 8259A, targeting cost-sensitive, power-constrained, and thermally demanding embedded control systems built around 80x86 and 8080/85 architectures.

FAQ

What is the operating voltage range for IS82C59AZX96?

The IS82C59AZX96 operates exclusively from a single +5V supply, with strict tolerance requirements aligned to TTL logic standards. It does not support wide-input voltage rails or dual-supply configurations. Decoupling with a 0.1μF capacitor between VCC (pin 28) and GND (pin 14) is mandatory per the datasheet to ensure noise immunity and stable interrupt vector timing. This fixed 5V requirement ensures interoperability with legacy 80x86 and MCS-80/85 bus systems.

Does IS82C59AZX96 support both edge-triggered and level-triggered interrupt inputs?

Yes, IS82C59AZX96 supports both edge-triggered and level-triggered operation on IR0–IR7 inputs. The mode is selected via the LTIM bit in ICW1: LTIM = 0 configures edge-triggered (low-to-high transition required), while LTIM = 1 enables level-triggered (sustained high level suffices). Internal pull-up resistors on all IR lines ensure defined logic states when unasserted, eliminating need for external biasing in either mode.

How many IS82C59AZX96 devices can be cascaded, and what is required to configure them?

Up to eight IS82C59AZX96 devices can be cascaded to manage 64 priority levels. One device operates as master (SP/EN = 1 or ICW4 M/S = 1), others as slaves (SP/EN = 0 or ICW4 M/S = 0). The master's CAS0–CAS2 outputs connect to corresponding slave CAS inputs. ICW3 must be issued to the master to identify which IR line connects to each slave, and to each slave to define its assigned ID (bits 2–0 matching its master IR number).

Is IS82C59AZX96 pin-compatible with the original NMOS 8259A?

Yes, IS82C59AZX96 is fully pin-compatible with the NMOS 8259A, sharing identical 28-pin PLCC pinout, signal definitions, and DC electrical characteristics. This allows direct replacement in existing designs without layout modification. However, IS82C59AZX96 offers lower power consumption (≤10μA standby), higher speed (12.5MHz vs. 8MHz typical for NMOS), and Pb-free construction - delivering functional equivalence with enhanced performance and compliance.

What microprocessor modes does IS82C59AZX96 support, and how are they selected?

IS82C59AZX96 supports two microprocessor modes: 8080/85 (CALL-based vectoring) and 80C86/88/286 (direct vector byte). Selection is made via the μPM bit in ICW4: μPM = 0 configures 8080/85 mode (three INTA pulses, delivers CALL opcode + low/high address bytes), while μPM = 1 configures 80C86/88/286 mode (two INTA pulses, delivers single 8-bit vector). Mode choice is software-configurable and may be changed dynamically during operation.