Renesas ISL22326UFR16Z
- Part No.:
- ISL22326UFR16Z
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 16-TFQFN Exposed Pad
- Datasheet:
-
ISL22326UFR16Z.pdf
- Description:
- IC DGTL POT 50KOHM 128TAP 16QFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,486
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ISL22326UFR16Z from Renesas Electronics is a dual digitally controlled potentiometer (XDCP™) with non-volatile wiper position storage, I²C interface, 128-tap resolution, and selectable 10kΩ or 50kΩ end-to-end resistance. It operates from 2.7V to 5.5V, supports shutdown mode (≤5µA), and is used for precision analog trimming in sensor calibration, power supply feedback loops, and audio level control.
For engineers reviewing the ISL22326UFR16Z datasheet, ISL22326UFR16Z pinout, ISL22326UFR16Z application, or ISL22326UFR16Z equivalent, key selection criteria include I²C address configurability (A0–A2), dual independent DCP operation, non-volatile initial value recall at power-up, wiper resistance (70Ω typ. @3.3V), and QFN-16 package compatibility with high-density PCB layouts.
Technical Context
The ISL22326UFR16Z integrates two independent 7-bit (128-position) digitally controlled potentiometers on a single monolithic CMOS die, each with volatile Wiper Register (WR) and non-volatile Initial Value Register (IVR). Wiper movement uses make-before-break CMOS switches across resistor ladders, ensuring monotonicity and glitch-free transitions.
It implements a full I²C slave interface compliant with standard-mode (≤400kHz) timing, supporting up to eight devices per bus via three hardware address pins (A0–A2). Shutdown is asserted either by logic-low SHDN pin or ACR register bit, placing RH/RW/RL terminals in open-circuit (RH–RL) and shorted (RW–RL) states respectively while preserving register accessibility.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total Resistance | 10kΩ (W option) or 50kΩ (U option); defines maximum adjustable range in voltage divider or rheostat configurations. |
| Resolution | 128 taps (7-bit WR); enables fine-grained analog adjustment with ≤0.78% step size relative to full scale. |
| Wiper Resistance | 70Ω typical at VCC = 3.3V; impacts signal integrity and loading in low-impedance circuits. |
| Supply Range | 2.7V to 5.5V; supports direct integration into 3.3V and 5V systems without level-shifting. |
| Shutdown Current | ≤5µA max at +85°C; enables ultra-low-power standby in battery-operated instrumentation. |
| Non-volatile Endurance | 1,000,000 write cycles per register; ensures long-term reliability in field-programmable calibration applications. |
| Temperature Coefficient | ±50 ppm/°C (10kΩ) or ±80 ppm/°C (50kΩ); guarantees stable resistance over -40°C to +125°C industrial range. |
Pinout & Package
ISL22326UFR16Z is packaged in a 16-lead QFN (4mm × 4mm, 0.5mm pitch) with exposed thermal pad internally connected to GND. Pin 1 is located at top-left corner (marked dot), and the package is RoHS-compliant and Pb-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power supply input | Supplies core logic and DCP array; must be decoupled locally to minimize noise coupling into analog paths. |
| GND | Ground reference | Common return for digital and analog sections; EPAD connection improves thermal performance and reduces ground bounce. |
| RH0, RL0, RW0 | DCP0 high/low/wiper terminals | Form first 3-terminal potentiometer or 2-terminal rheostat; RH0/RL0 define end-to-end resistance, RW0 provides adjustable tap. |
| RH1, RL1, RW1 | DCP1 high/low/wiper terminals | Independent second potentiometer; enables dual-channel trimming (e.g., gain + offset) without inter-channel crosstalk. |
| SCL / SDA | I²C clock/data bidirectional lines | Open-drain interfaces requiring external pull-ups; support multi-master arbitration and standard-mode timing (≤400kHz). |
| A0, A1, A2 | I²C device address inputs | Set LSBs of 7-bit slave address; allow up to eight ISL22326 devices on same bus without address conflict. |
| SHDN | Active-low shutdown control | Hardware override for power gating; forces RH–RL open and RW–RL short while retaining register access via I²C. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent DCPs | Enables simultaneous calibration of two analog parameters (e.g., VREF and ISET) with no shared timing or register dependencies. |
| Non-volatile IVR storage | Recalls last-trimmed wiper positions at power-on, eliminating need for host MCU re-initialization or factory recalibration. |
| Make-before-break switching | Prevents open-circuit glitches during wiper transitions, critical for maintaining loop stability in closed-loop power supplies. |
| I²C address flexibility | Three hardware-configurable address bits (A0–A2) simplify system-level integration in multi-device sensor or power modules. |
| Low wiper resistance | 70Ω typical ensures minimal insertion loss and signal attenuation in high-precision voltage divider applications. |
Applications
| Industrial Sensor Calibration | Programmable Power Supply Feedback |
|---|---|
|
Use Scenario: Trimming offset/gain in RTD, thermocouple, or bridge-sensor signal chains within programmable logic controllers. IC Role / Device Role / Timing Role: Dual DCP acts as precision analog front-end trim network, replacing mechanical pots and reducing field drift. Use Value: Non-volatile IVR retains calibrated values across power cycles, enabling unattended operation in remote monitoring nodes. |
Use Scenario: Adjusting output voltage and current limit thresholds in digitally controlled DC-DC converters and lab-grade PSUs. IC Role / Device Role / Timing Role: Replaces fixed resistive dividers in feedback networks, allowing dynamic setpoint changes via I²C. Use Value: 128-tap resolution supports <1% output accuracy; shutdown mode disables feedback path during fault conditions. |
| Audio Level Control | Medical Instrumentation Gain Setting |
|
Use Scenario: Volume and balance adjustment in professional audio mixers and embedded voice interfaces. IC Role / Device Role / Timing Role: Dual DCP configures left/right channel attenuation independently with matched tracking. Use Value: ≤2 LSB DNL and monotonic response prevent audible stepping artifacts; low wiper resistance preserves SNR. |
Use Scenario: Calibrating gain stages in ECG amplifiers, pulse oximeters, and portable diagnostic equipment. IC Role / Device Role / Timing Role: Provides traceable, repeatable analog trimming under ISO 13485-compliant manufacturing workflows. Use Value: 50-year data retention at <+55°C ensures calibration validity over product lifetime without recalibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5242BRUZ10 | Single 256-tap DCP, SPI interface, 10kΩ only, no shutdown pin, 14-TSSOP package. | Lacks dual-channel capability and hardware shutdown; requires SPI host instead of I²C. | Select when higher resolution (256 taps) is prioritized over dual-channel operation and I²C compatibility. |
| MCP45HV51-103E/ST | Dual 7-bit DCP, I²C interface, 10kΩ, 5.5V tolerant, but no non-volatile storage or shutdown pin. | Requires external EEPROM for power-up recall; no hardware SHDN control for analog isolation. | Choose for high-voltage (up to 36V) rheostat use where non-volatility is managed externally. |
Compared with AD5242BRUZ10 and MCP45HV51-103E/ST, the ISL22326UFR16Z uniquely combines dual DCPs, I²C address flexibility, hardware shutdown, and guaranteed non-volatile recall - making it optimal for space-constrained, self-calibrating industrial systems requiring zero-host intervention at startup.
Availability
ISL22326UFR16Z is available at Aetrix Electronics and suitable for industrial sensor calibration, programmable power supply feedback, and medical instrumentation gain setting requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for ISL22326UFR16Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog power, and mixed-signal solutions for industrial, automotive, and infrastructure markets.
The ISL22326UFR16Z belongs to Renesas' XDCP™ family of digitally controlled potentiometers, designed specifically for high-reliability analog trimming in harsh environments where mechanical potentiometers fail due to wear, vibration, or contamination.
FAQ
What is the default wiper position of ISL22326UFR16Z at power-up?
At initial power-on before non-volatile recall completes, both wipers default to position 40h (64 decimal), placing them near the midpoint of their respective resistor arrays. Once VCC exceeds the power-on reset threshold (2.0–2.6V), the contents of the Initial Value Registers (IVRs) are loaded into the Wiper Registers (WRs), restoring the last-saved positions. This behavior is confirmed in Section 5.1 and Table 2.1 of the FN6176 datasheet for ISL22326UFR16Z.
Does ISL22326UFR16Z support true dual-channel independent operation?
Yes, ISL22326UFR16Z provides fully independent control of DCP0 (RH0/RL0/RW0) and DCP1 (RH1/RL1/RW1) via separate I²C register addresses (00h and 01h for WR access). Each has its own volatile Wiper Register and non-volatile Initial Value Register, enabling simultaneous, uncorrelated adjustments - critical for applications like differential gain/offset trimming. This independence is explicitly defined in Sections 4.1 and 5.1 of the ISL22326UFR16Z datasheet.
How does the SHDN pin affect analog functionality in ISL22326UFR16Z?
When SHDN is pulled low, ISL22326UFR16Z places RHi–RLi in open-circuit and shorts RWi to RLi for both DCPs - effectively disabling analog signal paths while preserving register state and I²C accessibility. This hardware-controlled isolation prevents leakage or unintended biasing in powered-down subsystems. The behavior is detailed in Figure 18 and Section 4.1.3 of the ISL22326UFR16Z datasheet.
What is the maximum I²C clock frequency supported by ISL22326UFR16Z?
The ISL22326UFR16Z supports standard-mode I²C operation up to 400kHz, as specified in Section 2.5 (Serial Interface Specifications) of the datasheet. Timing parameters including tLOW (1300ns min), tHIGH (600ns min), and tSU:STA (600ns min) are validated for reliable communication at this rate. Exceeding 400kHz may violate setup/hold margins and cause register access failures in ISL22326UFR16Z.
Can ISL22326UFR16Z be used in rheostat mode, and what are the key limitations?
Yes, ISL22326UFR16Z supports rheostat configuration by connecting either RH or RL to RW (e.g., RW–RL for variable resistance). Key limitations include ±0.5 LSB DNL (U option) and ±1 LSB DNL (W option) in this mode, plus wiper resistance (70Ω typ.) contributing directly to total resistance. These values are measured and specified in Section 2.4 (Analog Specifications) of the ISL22326UFR16Z datasheet.
ISL22326UFR16Z Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 16-TFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 2
- Number of Taps:
- 128
- Resistance (Ohms):
- 50k
- Interface:
- I2C
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- 2.7V ~ 5.5V
- Features:
- Selectable Address
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- ±80ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 16-QFN (4x4)
- Operating Temperature:
- -40°C ~ 125°C
- Resistance - Wiper (Ohms) (Typ):
- 70
ISL22326UFR16Z FAQ
1.How can I place an order for ISL22326UFR16Z through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL22326UFR16Z on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL22326UFR16Z reliable?
The price and inventory of ISL22326UFR16Z are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL22326UFR16Z is usually 5 days.
3.What payment methods are accepted for ISL22326UFR16Z?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL22326UFR16Z transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL22326UFR16Z?
ISL22326UFR16Z orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL22326UFR16Z order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL22326UFR16Z?
For technical support, including ISL22326UFR16Z datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL22326UFR16Z requirements.
6.How does Aetrix verify that ISL22326UFR16Z is sourced from the original manufacturer or authorized distributors?
All ISL22326UFR16Z products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL22326UFR16Z meets industry standards.
7.What is the process for return or replacement of ISL22326UFR16Z?
All ISL22326UFR16Z units undergo pre-shipment inspection (PSI). If there is an issue with ISL22326UFR16Z, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL22326UFR16Z part is unused and in its original packaging.
Return procedure for ISL22326UFR16Z:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ISL22326UFR16Z Tags

-
MCP4018T-103E/LT
Microchip Technology

-
MCP4018T-503E/LT
Microchip Technology

-
MCP4011T-103E/SN
Microchip Technology

-
MCP4018T-104E/LT
Microchip Technology

-
MCP4017T-503E/LT
Microchip Technology

-
MCP4018T-502E/LT
Microchip Technology

-
MCP4017T-103E/LT
Microchip Technology

-
MCP4531T-103E/MF
Microchip Technology

-
MCP4021T-202E/SN
Microchip Technology

-
MCP4023T-103E/CH
Microchip Technology

-
MCP4022T-503E/CH
Microchip Technology

-
MCP4551T-502E/MS
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

