Renesas ISL23325TFVZ-TK
- Part No.:
- ISL23325TFVZ-TK
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
ISL23325TFVZ-TK.pdf
- Description:
- IC DGT POT 100KOHM 256TP 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL23325TFVZ-TK from Renesas Electronics is a dual, volatile, 256-tap digitally controlled potentiometer (DCP) with I²C interface, 100kΩ total resistance, ±2% end-to-end tolerance, and operation from 1.7V to 5.5V VCC and 1.2V to 5.5V VLOGIC. It delivers 70Ω typical wiper resistance at 3.3V and supports -40°C to +125°C industrial temperature range. It is used for precision gain adjustment in battery-powered instrumentation.
For engineers reviewing the ISL23325TFVZ-TK datasheet, ISL23325TFVZ-TK pinout, ISL23325TFVZ-TK application, or ISL23325TFVZ-TK equivalent, key selection considerations include dual-channel independent wiper control, 1.2V logic compatibility without level shifters, shutdown mode with internal RL connection, low 1.2µA standby current at 1.7V/1.2V, and 16-lead µTQFN package with 2.6mm × 1.8mm footprint.
Technical Context
The ISL23325TFVZ-TK integrates two independent DCP cores on a monolithic CMOS die, each with an 8-bit volatile Wiper Register (WR0/WR1) directly accessible via I²C. Wiper positioning uses make-before-break CMOS switches across 256 resistor taps, ensuring monotonicity and glitch-free transitions.
Its dual power domains isolate analog (VCC) and digital (VLOGIC) supplies, enabling direct interfacing with 1.2V microcontrollers while supporting up to 5.5V analog rail. Shutdown mode forces open-circuit end-to-end resistance and connects RW to RL through a 2kΩ path, reducing system leakage and power consumption.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total Resistance | 100kΩ - sets full-scale voltage divider ratio and current limiting capability in rheostat mode |
| Wiper Resistance | 70Ω typical @ 3.3V - minimizes insertion error in precision signal path applications |
| Supply Range (VCC) | 1.7V to 5.5V - enables use in ultra-low-voltage battery systems and standard 3.3V/5V rails |
| Logic Supply (VLOGIC) | 1.2V to 5.5V - eliminates need for external level shifters when interfacing with sub-1.8V MCUs |
| Standby Current | 1.2µA @ VCC=1.7V/VLOGIC=1.2V - extends battery life in always-on sensor nodes |
| Temperature Range | -40°C to +125°C - supports under-hood automotive and industrial motor control environments |
| End-to-End Tolerance | ±2% - ensures predictable gain scaling without per-unit calibration |
Pinout & Package
ISL23325TFVZ-TK is housed in a 16-lead, 2.6mm × 1.8mm, 0.5mm pitch µTQFN package (RoHS compliant, MSL3). Pinout is validated per FN7870 Rev 1.00, Page 2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND | Ground reference | Common return for analog and digital sections; must be low-impedance for noise-sensitive DCP operation |
| VLOGIC | Digital supply input | Powers I²C interface and address decoding logic; sets logic threshold levels independently of VCC |
| SDA | I²C bidirectional data line | Open-drain output requiring external pull-up; transmits ACK/NACK and register data |
| SCL | I²C clock input | Master-generated clock synchronizing all register reads/writes and wiper updates |
| A0–A2 | Slave address inputs | Hardwired LSBs of 7-bit I²C address; enable up to eight devices on same bus without software configuration |
| RH0, RL0, RW0 | DCP0 high/low/wiper terminals | Form first 3-terminal potentiometer or 2-terminal rheostat; RH0 and RL0 define full-scale resistance range |
| RH1, RL1, RW1 | DCP1 high/low/wiper terminals | Independent second DCP channel; supports dual-loop biasing or stereo gain control |
| VCC | Analog supply input | Powers resistor array and wiper switches; voltage defines maximum DCP terminal swing (0 to VCC) |
Key Features
| Feature | Design Value |
|---|---|
| Dual 256-tap DCPs | Enables simultaneous independent adjustment of two analog paths-e.g., differential amplifier gain and offset compensation |
| Volatile Wiper Registers (WR0/WR1) | Allows dynamic real-time tuning via I²C; power-on default to mid-scale (128) ensures known startup state |
| 1.2V–5.5V VLOGIC support | Direct interface with modern ultra-low-voltage MCUs (e.g., ARM Cortex-M0+) without level-shifting circuitry |
| Shutdown mode with RW–RL connection | Reduces system leakage by disconnecting DCP resistive elements while preserving wiper position state |
| ±2% end-to-end resistance tolerance | Minimizes unit-to-unit variation in closed-loop calibration schemes, reducing factory trim effort |
Applications
| Power Supply Margining | RF Power Amplifier Bias Compensation |
|---|---|
Use Scenario: Adjusting feedback resistor ratios in DC/DC converter voltage references to validate stability margins across voltage/temp corners. IC Role / Device Role / Timing Role: Dual DCP provides independent high-side and low-side resistor trimming for precise VOUT setpoint control. Use Value: Eliminates manual potentiometer replacement during production test; enables automated margining sweeps via I²C host. | Use Scenario: Dynamically compensating for temperature-induced drift in GaAs FET bias networks to maintain constant output power. IC Role / Device Role / Timing Role: ISL23325TFVZ-TK acts as programmable bias voltage divider, with one DCP setting gate voltage and the other adjusting source degeneration. Use Value: Achieves <±0.5dB RF output stability over -40°C to +125°C using factory-calibrated lookup tables stored in MCU. |
| Trimming Sensor Circuits | Gain Adjustment in Battery-Powered Instruments |
Use Scenario: Calibrating zero-offset and full-scale gain of MEMS pressure sensor signal chains during final test. IC Role / Device Role / Timing Role: ISL23325TFVZ-TK serves as precision programmable resistor in instrumentation amplifier feedback loop and reference divider. Use Value: Enables one-time digital calibration per unit; replaces two mechanical trimpots, saving board space and assembly cost. | Use Scenario: Setting audio codec PGA gain in portable ECG monitor to optimize SNR across varying electrode contact impedances. IC Role / Device Role / Timing Role: Dual-channel DCP configures both microphone preamp gain and ADC reference scaling in low-power sleep/wake cycles. Use Value: Delivers 70Ω wiper resistance and 1.2µA standby current-critical for >72-hour battery runtime in Class II medical devices. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5175BRMZ-100 | Single-channel, 256-tap, SPI interface, 100kΩ, 20ppm/°C tempco, 45Ω wiper R | Lacks dual DCP integration; requires separate ICs for multi-channel trimming | Choose when SPI-native host architecture exists and single-channel adjustment suffices |
| MCP45HV51-103E/MS | Dual-channel, 256-tap, I²C, 10kΩ, 100V tolerant, 125ppm/°C tempco, no VLOGIC independence | Supports higher voltage rails but lacks 1.2V logic compatibility and has looser resistance tolerance (±20%) | Prefer for high-voltage industrial controls where VLOGIC = VCC simplifies supply design |
Compared with AD5175BRMZ-100 and MCP45HV51-103E/MS, the ISL23325TFVZ-TK uniquely combines dual 100kΩ DCPs, 1.2V–5.5V VLOGIC independence, ±2% resistance tolerance, and 70Ω wiper resistance-making it optimal for compact, low-power, multi-parameter calibration in space-constrained embedded systems.
Availability
ISL23325TFVZ-TK is available at Aetrix Electronics and suitable for power supply margining, RF amplifier biasing, sensor trimming, and battery-powered instrument gain control requiring stable component supply across extended temperature and voltage ranges.
Supply support for ISL23325TFVZ-TK includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering microcontrollers, analog, power, and connectivity solutions for automotive, industrial, infrastructure, and IoT applications.
The ISL23325TFVZ-TK belongs to Renesas' precision analog XDCP™ (eXternally Digitally Controlled Potentiometer) product line, designed specifically for replacing mechanical potentiometers in automated calibration, adaptive biasing, and programmable gain control systems.
FAQ
What is the default wiper position of the ISL23325TFVZ-TK at power-on?
At power-on, both wiper registers (WR0 and WR1) of the ISL23325TFVZ-TK reset to 0x80 (128 decimal), positioning each wiper at mid-scale-exactly 50% of the 100kΩ total resistance between RH and RL terminals. This behavior is guaranteed across the full -40°C to +125°C operating range and ensures a known, repeatable startup state for deterministic system initialization.
Does the ISL23325TFVZ-TK support true 1.2V I²C bus operation without level shifting?
Yes, the ISL23325TFVZ-TK supports true 1.2V I²C operation via its dedicated VLOGIC pin, which powers the digital interface and internal level shifter. When VLOGIC = 1.2V, the SDA and SCL input thresholds scale accordingly (VIH = 0.7 × VLOGIC ≈ 0.84V), and the device draws only 5µA ILOGIC during active communication-enabling direct connection to 1.2V microcontrollers without external translation circuitry.
How does shutdown mode affect the wiper position and DCP terminals in the ISL23325TFVZ-TK?
In shutdown mode (SHDN bit = 0 in ACR register), the ISL23325TFVZ-TK disconnects both DCP resistor arrays from the circuit, forcing RH–RL open-circuit. Simultaneously, each wiper (RW0/RW1) is internally connected to its respective RL terminal through a 2kΩ resistor. Wiper register values are retained, and the device exits shutdown with the prior tap positions restored after ≤1.5µs recall time.
What is the maximum allowable wiper current for the ISL23325TFVZ-TK, and how is it enforced?
The ISL23325TFVZ-TK specifies a maximum continuous wiper current (IW) of ±3mA under recommended operating conditions. This limit is enforced by the internal CMOS switch on-resistance and thermal design margin-not by active current limiting. Exceeding ±3mA risks accelerated wear or parametric shift; for higher-current applications, external series resistors or buffer amplifiers must be used to constrain IW within specification.
Can the ISL23325TFVZ-TK be used in rheostat (two-terminal) mode, and what are the key non-linearity specs?
Yes, the ISL23325TFVZ-TK supports rheostat mode by connecting either RH or RL to the wiper (RW) and using the remaining two terminals. For 100kΩ option, integral non-linearity (RINL) is ±1.0 MI and differential non-linearity (RDNL) is ±0.15 MI over 2.7V–5.5V VCC-ensuring monotonic response and predictable step resolution in programmable current-source or filter-tuning applications.
ISL23325TFVZ-TK Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 2
- Number of Taps:
- 256
- Resistance (Ohms):
- 100k
- Interface:
- I2C
- Memory Type:
- Volatile
- Voltage - Supply:
- 1.2V ~ 5.5V, 1.7V ~ 5.5V
- Features:
- Selectable Address
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- 45ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 14-TSSOP
- Operating Temperature:
- -40°C ~ 125°C
- Resistance - Wiper (Ohms) (Typ):
- 70
ISL23325TFVZ-TK FAQ
1.How can I place an order for ISL23325TFVZ-TK through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL23325TFVZ-TK on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL23325TFVZ-TK reliable?
The price and inventory of ISL23325TFVZ-TK are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL23325TFVZ-TK is usually 5 days.
3.What payment methods are accepted for ISL23325TFVZ-TK?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL23325TFVZ-TK transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL23325TFVZ-TK?
ISL23325TFVZ-TK orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL23325TFVZ-TK order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL23325TFVZ-TK?
For technical support, including ISL23325TFVZ-TK datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL23325TFVZ-TK requirements.
6.How does Aetrix verify that ISL23325TFVZ-TK is sourced from the original manufacturer or authorized distributors?
All ISL23325TFVZ-TK products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL23325TFVZ-TK meets industry standards.
7.What is the process for return or replacement of ISL23325TFVZ-TK?
All ISL23325TFVZ-TK units undergo pre-shipment inspection (PSI). If there is an issue with ISL23325TFVZ-TK, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL23325TFVZ-TK part is unused and in its original packaging.
Return procedure for ISL23325TFVZ-TK:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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