Renesas ISL23325UFRUZ-TK
- Part No.:
- ISL23325UFRUZ-TK
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 16-UFQFN
- Datasheet:
-
ISL23325UFRUZ-TK.pdf
- Description:
- IC DGT POT 50KOHM 256TAP 16UTQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL23325UFRUZ-TK from Renesas Electronics (formerly Intersil) is a dual, volatile, 256-tap digitally controlled potentiometer with I²C interface, designed for precision analog adjustment in low-voltage systems. It features two independent 50kΩ DCPs, 1.2V–5.5V logic supply (VLOGIC), 1.7V–5.5V analog supply (VCC), and operates across –40°C to +125°C - used in battery-powered sensor trimming and power supply margining.
For engineers reviewing the ISL23325UFRUZ-TK datasheet, ISL23325UFRUZ-TK pinout, ISL23325UFRUZ-TK application, or ISL23325UFRUZ-TK equivalent, key selection criteria include dual-channel wiper register control, shutdown mode behavior, 16-lead µTQFN package compatibility, and verified 50kΩ end-to-end resistance with ±2% tolerance at +25°C.
Technical Context
The ISL23325UFRUZ-TK integrates two monolithic CMOS DCP cores with make-before-break wiper switching, each controlled by an 8-bit volatile Wiper Register (WR0/WR1). Its I²C interface supports up to 400kHz clock rate, three address pins (A0–A2), and independent VLOGIC/VCC rails enabling direct interfacing with 1.2V microcontrollers without level shifters.
Each DCP operates in voltage divider or rheostat mode; wiper position defaults to mid-scale (128) on power-up. Shutdown mode disconnects RH–RL paths and connects RW to RL via internal 2kΩ resistor, reducing leakage and power consumption while preserving WR values.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total Resistance | 50kΩ per DCP - defines full-scale analog range for gain/offset tuning in sensor and power circuits. |
| Tap Count | 256 steps - enables 0.39% resolution per step in voltage divider mode (e.g., 12.5mV/step @ 3.2V span). |
| VLOGIC Range | 1.2V to 5.5V - allows direct connection to ultra-low-voltage MCUs (e.g., ARM Cortex-M0+) without external level translation. |
| Wiper Resistance | 70Ω typical @ 3.3V - minimizes signal path error in precision voltage division and feedback networks. |
| Temp Range | –40°C to +125°C - qualified for under-hood automotive, industrial motor control, and high-reliability embedded systems. |
| Shutdown Current | 1.2µA @ VCC=1.7V/VLOGIC=1.2V - enables microamp-level system sleep states in portable instrumentation. |
| INL (Voltage Mode) | ±0.15 LSB max (50kΩ option) - ensures monotonicity and <0.06% absolute linearity error over full tap range. |
Pinout & Package
ISL23325UFRUZ-TK uses a 16-lead 2.6mm × 1.8mm µTQFN package (RoHS-compliant, e4 NiPdAu termination), optimized for space-constrained PCB layouts and automated assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A2 | I²C slave address inputs | Hardwired to VLOGIC or GND to select one of eight unique addresses on shared bus. |
| SDA | I²C bidirectional data line | Open-drain output requires external pull-up; supports standard/fast-mode I²C up to 400kHz. |
| SCL | I²C clock input | Accepts 1.2V–5.5V logic levels; timing compliant with I²C specification (tLOW ≥1300ns, tHIGH ≥600ns). |
| VLOGIC | Digital supply reference | Defines logic threshold for all digital pins; decoupled from VCC to enable mixed-supply systems. |
| VCC | Analog supply input | Powers DCP resistor array and wiper switches; must be ≥ VDCP terminal voltages (0 to VCC). |
| GND | Analog/digital common reference | Single ground plane required; no separate AGND/DGND pins - layout must minimize noise coupling. |
| RH0, RL0, RW0 | DCP0 high/low/wiper terminals | Form first 3-terminal potentiometer; RW0 position set by WR0 register (0–255 decimal). |
| RH1, RL1, RW1 | DCP1 high/low/wiper terminals | Independent second potentiometer; identical electrical specs and control as DCP0. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 50kΩ DCPs in single µTQFN | Reduces board area vs. discrete pots or dual TSSOP alternatives; eliminates inter-channel drift mismatch. |
| Volatile wiper registers (WR0/WR1) | Enables dynamic real-time adjustment via firmware; no EEPROM wear-out or write-cycle delays. |
| Independent VLOGIC/VCC supplies | Supports 1.2V I²C masters (e.g., MSP430FRxx) interfacing with 5V analog subsystems without level shifters. |
| Shutdown mode with RW–RL tie | Prevents floating wiper outputs during sleep; maintains known impedance state (RW connected to RL via 2kΩ) for safe system reset. |
| Power-on default to mid-scale (128) | Guarantees predictable startup behavior - avoids transient over/under-shoot in closed-loop bias or gain circuits. |
Applications
| Power Supply Margining | Sensor Circuit Trimming |
|---|---|
Use Scenario: Adjusting reference voltage thresholds in DC-DC converter feedback loops to validate stability margins across voltage/temp corners. IC Role / Device Role / Timing Role: Dual DCP provides independent high-side and low-side resistor ratio control in resistive divider networks feeding error amplifiers. Use Value: Enables automated production test margining without manual potentiometer adjustment; 50kΩ value matches typical FB network impedances for minimal loading error. | Use Scenario: Calibrating offset/gain in bridge-based pressure or temperature sensors before ADC digitization. IC Role / Device Role / Timing Role: One DCP sets zero-point offset (series with sensor leg), the other adjusts full-scale gain (in amplifier feedback path). Use Value: 256-step resolution supports <±0.1% calibration accuracy; ±0.15 LSB INL ensures monotonic correction across operating temperature. |
| RF Power Amplifier Bias | Battery-Powered Instrument Gain Control |
Use Scenario: Dynamically tuning gate/base bias voltage of GaAs or Si LDMOS PAs to maintain linearity and efficiency across output power levels. IC Role / Device Role / Timing Role: DCP configured as rheostat between bias supply and PA input; wiper position adjusted by baseband controller via I²C. Use Value: 70Ω typical wiper resistance minimizes insertion loss; 1.2V VLOGIC support enables direct interface with low-power RF SoCs. | Use Scenario: Setting programmable gain in handheld multimeters or portable oscilloscope front-ends powered by single-cell Li-ion batteries. IC Role / Device Role / Timing Role: Dual DCPs configure variable-gain transimpedance and buffer stages; VCC scaled to battery voltage (1.7V–4.2V). Use Value: 1.2µA shutdown current extends battery life; 50kΩ resistance optimizes noise-vs-bandwidth tradeoff in op-amp feedback networks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL23325TFRUZ-TK | Same package and pinout; 100kΩ total resistance instead of 50kΩ. | Better suited for high-impedance bias networks where lower current draw is critical; higher TCv (2.3 ppm/°C vs. 4 ppm/°C) improves ratiometric stability. | Select when circuit requires >50kΩ resistance to reduce power dissipation or improve noise immunity in high-Z nodes. |
| MCP42050-I/SL | Microchip dual 50kΩ DCP in 14-lead SOIC; SPI interface only; no VLOGIC pin - VDD powers both logic and analog sections. | Lacks independent logic/analog supplies; limited to 2.7V–5.5V operation; no 1.2V bus compatibility. | Choose for cost-sensitive, non-battery applications where SPI is preferred and mixed-voltage I²C is unnecessary. |
Compared with ISL23325TFRUZ-TK, the ISL23325UFRUZ-TK offers lower end-to-end resistance for reduced thermal noise and higher current drive capability, while MCP42050-I/SL trades I²C flexibility and ultra-low-voltage support for simpler supply architecture and broader distributor availability.
Availability
ISL23325UFRUZ-TK is available at Aetrix Electronics and suitable for power supply margining, sensor trimming, RF bias compensation, and battery-powered instrument gain control requiring stable component supply across extended temperature ranges.
Supply support for ISL23325UFRUZ-TK includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics acquired Intersil in 2017 and maintains full technical and manufacturing continuity for the ISL23325 family.
The ISL23325 product line delivers precision, low-voltage digitally controlled potentiometers targeting battery-operated equipment, industrial sensing, and automotive subsystems requiring extended temperature operation and mixed-supply robustness.
FAQ
What is the total resistance value of the ISL23325UFRUZ-TK?
The ISL23325UFRUZ-TK has a nominal total resistance of 50kΩ per potentiometer channel (RH0–RL0 and RH1–RL1), with a guaranteed tolerance of ±2% at +25°C and –20% to +20% over temperature. This value is fixed per device variant and confirmed in the Ordering Information table of FN7870 Rev 1.00.
Does the ISL23325UFRUZ-TK retain wiper settings after power cycling?
No - the ISL23325UFRUZ-TK uses volatile wiper registers (WR0 and WR1). Upon power-up, both wipers reset to mid-scale (128 decimal), as specified in the "Principles of Operation" section. Non-volatile storage requires external MCU firmware to reinitialize positions after reset.
Can the ISL23325UFRUZ-TK operate with a 1.2V I²C bus while VCC is at 3.3V?
Yes - the ISL23325UFRUZ-TK supports independent VLOGIC (1.2V–5.5V) and VCC (1.7V–5.5V) supplies. With VLOGIC = 1.2V and VCC = 3.3V, the I²C interface remains fully functional per specification, including valid VIH/VIL thresholds and SDA/SCL timing compliance at 400kHz.
What happens to the wiper terminals during shutdown mode of the ISL23325UFRUZ-TK?
In shutdown mode (SHDN bit = 0 in ACR), each DCP is forced into an end-to-end open circuit, and the wiper (RW0/RW1) is internally connected to its respective low terminal (RL0/RL1) through a 2kΩ resistor. This prevents floating outputs and maintains a defined impedance state while minimizing current draw.
Is the ISL23325UFRUZ-TK pin-compatible with other variants in the ISL23325 family?
Yes - all ISL23325 variants sharing the "UFRUZ" suffix (e.g., ISL23325UFRUZ-TK, ISL23325UFRUZ-T7A) use the identical 16-lead µTQFN package and pinout. Resistance value (50kΩ), temperature range (–40°C to +125°C), and electrical specifications are consistent across these variants; only tape-and-reel packaging differs.
ISL23325UFRUZ-TK Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 16-UFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 2
- Number of Taps:
- 256
- Resistance (Ohms):
- 50k
- Interface:
- I2C
- Memory Type:
- Volatile
- Voltage - Supply:
- 1.2V ~ 5.5V, 1.7V ~ 5.5V
- Features:
- Selectable Address
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- 65ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 16-UTQFN (2.6x1.8)
- Operating Temperature:
- -40°C ~ 125°C
- Resistance - Wiper (Ohms) (Typ):
- 70
ISL23325UFRUZ-TK FAQ
1.How can I place an order for ISL23325UFRUZ-TK through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL23325UFRUZ-TK on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL23325UFRUZ-TK reliable?
The price and inventory of ISL23325UFRUZ-TK are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL23325UFRUZ-TK is usually 5 days.
3.What payment methods are accepted for ISL23325UFRUZ-TK?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL23325UFRUZ-TK transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL23325UFRUZ-TK?
ISL23325UFRUZ-TK orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL23325UFRUZ-TK order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL23325UFRUZ-TK?
For technical support, including ISL23325UFRUZ-TK datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL23325UFRUZ-TK requirements.
6.How does Aetrix verify that ISL23325UFRUZ-TK is sourced from the original manufacturer or authorized distributors?
All ISL23325UFRUZ-TK products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL23325UFRUZ-TK meets industry standards.
7.What is the process for return or replacement of ISL23325UFRUZ-TK?
All ISL23325UFRUZ-TK units undergo pre-shipment inspection (PSI). If there is an issue with ISL23325UFRUZ-TK, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL23325UFRUZ-TK part is unused and in its original packaging.
Return procedure for ISL23325UFRUZ-TK:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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