Renesas ISL23345UFRZ
- Part No.:
- ISL23345UFRZ
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 20-VFQFN Exposed Pad
- Datasheet:
-
ISL23345UFRZ.pdf
- Description:
- IC DGTL POT 50KOHM 256TAP 20QFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,202
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Product details
Overview
ISL23345UFRZ from Renesas (formerly Intersil) is a volatile quad digitally controlled potentiometer (DCP) with I²C interface, 50 kΩ total resistance per channel, 256-tap resolution, and operation from 1.7V to 5.5V VCC and 1.2V to 5.5V VLOGIC. It integrates four independent DCP cores in a 20-lead 3×4 mm QFN package and is used for precision gain adjustment and sensor trimming in battery-powered instrumentation.
For engineers reviewing the ISL23345UFRZ datasheet, ISL23345UFRZ pinout, ISL23345UFRZ application, or ISL23345UFRZ equivalent, key selection considerations include its 50 kΩ resistance option, -40°C to +125°C extended industrial temperature range, shutdown mode with end-to-end open-circuit behavior, wiper resistance of 70 Ω typical at 3.3V, and support for multi-device I²C bus addressing via A0–A2 pins.
Technical Context
The ISL23345UFRZ implements four independent resistor arrays using CMOS switches in make-before-break configuration, each controlled by an 8-bit volatile Wiper Register (WR0–WR3). Wiper position is updated via I²C write commands, with power-on reset to mid-scale (128 decimal).
It features dual-supply architecture: VCC powers analog DCP circuitry (1.7–5.5 V), while VLOGIC supplies logic and I²C interface (1.2–5.5 V), enabling direct connection to low-voltage microcontrollers without level shifters. Shutdown mode disconnects all DCP resistors and internally connects each RWi to RLi through a 2 kΩ resistor.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total Resistance | 50 kΩ per DCP channel - sets full-scale voltage divider ratio and current handling capability in rheostat mode. |
| Tap Resolution | 256 taps (8-bit) - enables 0.39% step resolution for fine analog control in trimming applications. |
| VCC Range | 1.7 V to 5.5 V - supports single-supply operation across Li-ion, 3.3 V, and 5 V systems. |
| VLOGIC Range | 1.2 V to 5.5 V - allows direct interfacing with 1.2 V, 1.8 V, or 3.3 V I²C masters without external level translation. |
| Wiper Resistance | 70 Ω typical at VCC = 3.3 V - minimizes signal path error in precision voltage divider configurations. |
| Temperature Range | -40°C to +125°C - qualified for automotive under-hood, industrial motor control, and harsh-environment embedded systems. |
| Shutdown Current | 1.5 µA VCC / 0.5 µA VLOGIC at 1.7 V - enables ultra-low-power sleep states in portable equipment. |
Pinout & Package
ISL23345UFRZ is housed in a 20-lead 3×4 mm Pb-free QFN package with exposed thermal pad. Pin functions are electrically identical to the TSSOP variant but differ in physical layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RL0–RL3 | DCP0–DCP3 low terminals | Fixed endpoints of each potentiometer; referenced to GND or system low potential in voltage divider mode. |
| RW0–RW3 | DCP0–DCP3 wiper terminals | Movable output nodes; position determined by WR0–WR3 registers; connect to feedback or gain-setting nodes. |
| RH0–RH3 | DCP0–DCP3 high terminals | Fixed endpoints; typically connected to VCC, reference voltage, or signal source in divider/rheostat use. |
| VCC | Analog supply | Powers internal resistor arrays and CMOS switches; must be ≥ VDCP terminal voltages. |
| GND | Analog ground | Reference for all DCP terminals; requires low-impedance connection to minimize noise coupling. |
| VLOGIC | Digital supply | Powers I²C interface and address logic; independent of VCC; enables mixed-voltage system integration. |
| A0–A2 | I²C slave address inputs | Hardwired to VLOGIC or GND to select one of eight possible addresses on shared bus. |
| SDA/SCL | I²C bidirectional data/clock | Open-drain pins requiring external pull-ups; compliant with standard/fast-mode I²C (≤400 kHz). |
Key Features
| Feature | Design Value |
|---|---|
| Quad 256-tap DCPs in single QFN | Reduces board space and BOM count vs. discrete potentiometers or multiple single-channel ICs. |
| Volatile wiper registers (WR0–WR3) | Enables dynamic real-time adjustment of four independent analog parameters via I²C without nonvolatile memory overhead. |
| Independent VCC/VLOGIC supplies | Eliminates need for level shifters when interfacing with sub-1.8 V MCUs while powering DCPs from higher analog rails. |
| Shutdown mode with RW–RL tie | Forces safe open-circuit state and isolates DCPs from signal path during standby, reducing leakage and power consumption. |
| ±0.15 LSB DNL (U option) | Ensures monotonic response and predictable step-linearity in closed-loop gain calibration and sensor offset correction. |
| 1.2 V minimum VLOGIC | Supports integration into modern ultra-low-power IoT sensor nodes and wearables with 1.2 V domain logic. |
Applications
| Power Supply Margining | Sensor Circuit Trimming |
|---|---|
Use Scenario: Adjusting reference voltage thresholds in DC-DC converter feedback loops to validate stability margins across voltage/temp corners. IC Role / Device Role / Timing Role: Quad DCP provides independent, software-controlled trim of four different supply rails or feedback dividers simultaneously. Use Value: Enables automated production test margining without manual potentiometer adjustment; supports 50 kΩ impedance matching to common feedback networks. |
Use Scenario: Compensating offset and gain drift in bridge-based pressure or temperature sensors over -40°C to +125°C. IC Role / Device Role / Timing Role: Acts as programmable gain/offset element in instrumentation amplifier front-end; wiper registers updated via host MCU during calibration. Use Value: Achieves <±0.5 LSB INL and ±0.15 LSB DNL for high-accuracy trimming; 65 ppm/°C end-to-end tempco ensures stable performance across industrial temperature range. |
| Battery-Powered Instrument Gain Control | RF Power Amplifier Bias Compensation |
Use Scenario: Dynamically scaling gain in portable oscilloscopes or handheld multimeters to maintain signal fidelity across input ranges. IC Role / Device Role / Timing Role: Configured as voltage divider between signal path and ADC reference; updated in real time based on input amplitude detection. Use Value: 70 Ω typical wiper resistance minimizes loading error; 5 µA standby current extends battery life in always-on measurement modes. |
Use Scenario: Stabilizing quiescent current in GaAs/GaN RF PAs subject to thermal drift during transmit bursts. IC Role / Device Role / Timing Role: Used in bias network to adjust gate voltage dynamically; four channels support multi-stage PA bias control. Use Value: 256-tap resolution enables fine bias tuning; shutdown mode disables bias path during PA sleep cycles, preventing unintended conduction. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL23325UFRZ | Same quad 256-tap architecture, but 50 kΩ option with improved ±0.1 LSB DNL and lower 4 ppm/°C ratiometric tempco. | Targeted for higher-precision trimming where tighter linearity and temperature tracking are required. | Preferred when absolute monotonicity and ratiometric stability outweigh cost sensitivity; pin-compatible drop-in replacement. |
| AD5272BRUZ50 | Single-channel, 1024-tap, nonvolatile (EEPROM), 50 kΩ, SPI interface, 20-lead TSSOP. | Used where power-loss retention of wiper setting is mandatory; lacks quad integration and I²C compatibility. | Select when nonvolatile storage is critical and board space permits separate ICs per channel; not pin- or protocol-compatible. |
Compared with ISL23345UFRZ, ISL23325UFRZ offers superior linearity and temperature tracking for precision calibration, while AD5272BRUZ50 provides EEPROM retention at the cost of channel count, interface, and footprint efficiency.
Availability
ISL23345UFRZ is available at Aetrix Electronics and suitable for power supply margining, sensor trimming, battery-powered instrument gain control, and RF amplifier bias compensation requiring stable component supply across extended temperature and low-voltage operating conditions.
Supply support for ISL23345UFRZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation acquired Intersil in 2017 and continues to manufacture and support its precision analog portfolio, including digitally controlled potentiometers and interface ICs.
The ISL23345UFRZ belongs to Renesas' XDCP™ (eXternally Digitally Controlled Potentiometer) family, designed specifically for replacing mechanical pots in automated calibration, adaptive biasing, and programmable analog signal conditioning systems.
FAQ
What is the resistance tolerance and temperature coefficient of the ISL23345UFRZ?
The ISL23345UFRZ has a nominal total resistance of 50 kΩ with ±2% tolerance. Its end-to-end temperature coefficient is 65 ppm/°C over -40°C to +125°C, ensuring stable resistance values across industrial temperature ranges without requiring recalibration.
Does the ISL23345UFRZ retain wiper settings after power cycling?
No, the ISL23345UFRZ uses volatile wiper registers. Upon power-up, all four wipers reset to mid-scale (128 decimal). To restore a specific setting, the host MCU must reinitialize WR0–WR3 via I²C after power-on sequencing completes.
Can the ISL23345UFRZ operate with different VCC and VLOGIC voltages simultaneously?
Yes - the ISL23345UFRZ supports independent supplies: VCC (1.7–5.5 V) for analog DCP operation and VLOGIC (1.2–5.5 V) for digital interface. This allows direct connection to 1.2 V or 1.8 V MCUs while powering the DCPs from a 3.3 V or 5 V rail.
How many devices can share the same I²C bus with the ISL23345UFRZ?
Up to eight ISL23345UFRZ devices can coexist on a single I²C bus. Address bits A2, A1, and A0 are hardwired to VLOGIC or GND to configure unique 7-bit slave addresses, eliminating address conflicts in multi-channel systems.
What happens to the DCP terminals during shutdown mode?
In shutdown mode (SHDN bit = 0 in ACR register), each DCP channel enters an end-to-end open-circuit state, and the wiper (RWi) is internally connected to the low terminal (RLi) via a 2 kΩ resistor. This isolates the signal path while preserving WRi register contents for fast recovery.
ISL23345UFRZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 20-VFQFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 4
- Number of Taps:
- 256
- Resistance (Ohms):
- 50k
- Interface:
- I2C
- Memory Type:
- Volatile
- Voltage - Supply:
- 1.2V ~ 5.5V, 1.7V ~ 5.5V
- Features:
- Selectable Address
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- 65ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-QFN (3x4)
- Operating Temperature:
- -40°C ~ 125°C
- Resistance - Wiper (Ohms) (Typ):
- 70
ISL23345UFRZ FAQ
1.How can I place an order for ISL23345UFRZ through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL23345UFRZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL23345UFRZ reliable?
The price and inventory of ISL23345UFRZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL23345UFRZ is usually 5 days.
3.What payment methods are accepted for ISL23345UFRZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL23345UFRZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL23345UFRZ?
ISL23345UFRZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL23345UFRZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL23345UFRZ?
For technical support, including ISL23345UFRZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL23345UFRZ requirements.
6.How does Aetrix verify that ISL23345UFRZ is sourced from the original manufacturer or authorized distributors?
All ISL23345UFRZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL23345UFRZ meets industry standards.
7.What is the process for return or replacement of ISL23345UFRZ?
All ISL23345UFRZ units undergo pre-shipment inspection (PSI). If there is an issue with ISL23345UFRZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL23345UFRZ part is unused and in its original packaging.
Return procedure for ISL23345UFRZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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