Renesas ISL23425WFVZ-T7A
- Part No.:
- ISL23425WFVZ-T7A
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
ISL23425WFVZ-T7A.pdf
- Description:
- IC DGT POT 10KOHM 256TAP 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,574
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Product details
Overview
ISL23425WFVZ-T7A from Renesas Electronics (formerly Intersil) is a dual, volatile, 256-tap digitally controlled potentiometer (DCP) with SPI interface, 10kΩ end-to-end resistance, 14-lead TSSOP package, and -40°C to +125°C operation. It functions as two independent programmable resistive dividers or rheostats in low-power, battery-operated systems requiring precise analog trimming.
For engineers reviewing the ISL23425WFVZ-T7A datasheet, ISL23425WFVZ-T7A pinout, ISL23425WFVZ-T7A application, or ISL23425WFVZ-T7A equivalent, key selection criteria include its 10kΩ resistance option, 1.7V–5.5V VCC / 1.2V–5.5V VLOGIC dual-supply flexibility, 70Ω typical wiper resistance at 3.3V, shutdown mode with open-circuit DCP terminals, and guaranteed monotonicity in both voltage divider and rheostat modes.
Technical Context
The ISL23425WFVZ-T7A integrates two independent CMOS-switched resistor arrays on a monolithic die, each controlled by an 8-bit volatile Wiper Register (WR0/WR1). Its "make-before-break" switching ensures glitch-free wiper transitions during tap changes.
It implements SPI Mode 0 (CPOL = 0, CPHA = 0) with rising-edge data input and falling-edge data output, supporting daisy-chaining and no external level shifter required for 1.2V logic buses. The VLOGIC pin decouples digital interface supply from analog VCC, enabling mixed-voltage system integration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total Resistance | 10kΩ - defines full-scale analog range for gain/offset adjustment in sensor or amplifier circuits |
| Wiper Resistance | 70Ω typical @ 3.3V - limits insertion error and signal attenuation in precision voltage divider configurations |
| Supply Range | VCC = 1.7V–5.5V, VLOGIC = 1.2V–5.5V - enables direct interfacing with ultra-low-voltage MCUs without level translation |
| Standby Current | 4µA @ 5V, 1.7µA @ 1.7V - supports multi-year battery life in always-on instrumentation |
| Temperature Range | -40°C to +125°C - qualified for under-hood automotive, industrial control, and harsh-environment embedded systems |
| Integral Nonlinearity | ±0.5 LSB (voltage divider mode) - ensures ≤0.2% full-scale error across 256 taps for calibration-critical applications |
| Settling Time | 300ns large-signal wiper settling - supports dynamic reconfiguration in real-time feedback loops |
Pinout & Package
Package: 14-lead TSSOP (M14.173), Pb-free, RoHS compliant, 5.0mm × 4.4mm × 1.2mm profile.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Pins 1, 7) | Ground reference | Common return for analog and digital sections; requires low-impedance PCB connection to minimize noise coupling |
| VLOGIC (Pin 2) | Digital supply | Powers SPI interface logic independently of VCC; sets input thresholds and SDO drive strength |
| SDO (Pin 3) | SPI data output | Configurable Push-Pull or Open-Drain; outputs register reads on SCK falling edge |
| SCK (Pin 4) | SPI clock input | Rising edge clocks SDI data in; max 5MHz @ ≥1.7V VLOGIC, 1MHz @ 1.2–1.6V |
| SDI (Pin 5) | SPI data input | Receives instruction and data bytes; MSB-first, setup/hold times defined per VLOGIC level |
| CS (Pin 6) | Chip select | Active-low enable; HIGH places device in standby; rising edge triggers wiper recall from shutdown |
| RL1 (Pin 8) | DCP1 low terminal | Fixed end of second potentiometer array; connects to ground or signal reference in divider mode |
| RW1 (Pin 9) | DCP1 wiper | Programmable tap point; delivers adjustable voltage/resistance; 70Ω typical series impedance |
| RH1 (Pin 10) | DCP1 high terminal | Fixed end of second potentiometer array; connects to VCC or bias source in divider mode |
| RH0 (Pin 11) | DCP0 high terminal | Fixed end of first potentiometer array; used for gain-setting feedback in op-amp circuits |
| RW0 (Pin 12) | DCP0 wiper | Primary adjustment node for sensor offset trimming or power supply margining |
| RL0 (Pin 13) | DCP0 low terminal | Reference node for first potentiometer; tied to GND or virtual ground in active circuits |
| VCC (Pin 14) | Analog supply | Powers resistor arrays and wiper switches; must exceed max DCP terminal voltage (0–VCC) |
Key Features
| Feature | Design Value |
|---|---|
| Dual 256-tap DCPs | Enables simultaneous calibration of two independent analog paths (e.g., differential sensor channels) without board space penalty |
| Volatile wiper registers (WR0/WR1) | Allows dynamic runtime adjustment via SPI; power-on defaults to mid-scale (128) for safe startup |
| Independent VLOGIC supply | Eliminates need for external level shifters when interfacing with 1.2V/1.8V microcontrollers in mixed-voltage designs |
| Shutdown mode | Forces DCP terminals into open-circuit state and connects RWi to RLi via 2kΩ path-reduces leakage and isolates circuit during sleep |
| Monotonic performance | Guaranteed ±0.5 LSB INL and ±0.4 LSB DNL in voltage divider mode ensures predictable, stepwise analog response |
| Extended temperature grade | Validated operation from -40°C to +125°C supports deployment in automotive engine control units and industrial motor drives |
Applications
| Power Supply Margining | Trimming Sensor Circuits |
|---|---|
Use Scenario: Adjusting reference voltage inputs to DC-DC controllers during production test to verify regulation tolerance margins. IC Role / Device Role / Timing Role: Programmable voltage divider setting precise upper/lower bounds on feedback node voltage. Use Value: Enables automated, software-controlled margin testing without manual potentiometer replacement or soldering. | Use Scenario: Compensating offset drift in bridge-based pressure or temperature sensors over temperature and time. IC Role / Device Role / Timing Role: Two-terminal rheostat in op-amp offset null loop, dynamically tuned via host MCU. Use Value: Achieves <±1mV offset correction across -40°C to +125°C using factory-calibrated lookup tables stored in MCU flash. |
| Gain Adjustment in Battery Powered Instruments | RF Power Amplifier Bias Compensation |
Use Scenario: Scaling full-scale range of portable multimeters or handheld oscilloscopes based on selected measurement range. IC Role / Device Role / Timing Role: Three-terminal potentiometer in transimpedance amplifier feedback path. Use Value: Provides 256-step gain resolution (e.g., 1× to 1000×) with <0.2% linearity error, extending battery life via ultra-low 4µA standby current. | Use Scenario: Dynamically adjusting gate bias voltage of GaN or LDMOS RF PAs to maintain constant output power across temperature and aging. IC Role / Device Role / Timing Role: Voltage divider feeding PA bias FET gate, updated in real time via SPI from thermal sensor readings. Use Value: Compensates for >100ppm/°C VGS(th) drift using 120kHz –1200kHz bandwidth (10kΩ option), preserving EVM and efficiency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5242BRUZ10 | I²C interface only; 10kΩ; 16-lead TSSOP; 200ppm/°C tempco; no VLOGIC pin | Lacks independent logic supply-requires level shifter for sub-1.8V MCUs; higher tempco reduces precision in wide-temp environments | Select when I²C bus is preferred and system uses ≥1.8V logic; avoid for 1.2V–1.7V MCU interfaces or high-accuracy thermal compensation |
| MCP42010-I/P | Single-channel; 10kΩ; 14-lead PDIP; SPI interface; 100ppm/°C tempco; no shutdown mode | Half the channel count; through-hole package unsuitable for high-density layouts; no power-gating capability | Choose for cost-sensitive, low-channel-count designs where PCB real estate and power gating are not constraints |
Compared with AD5242BRUZ10 and MCP42010-I/P, the ISL23425WFVZ-T7A uniquely combines dual-channel operation, 1.2V logic compatibility, shutdown isolation, and 45–125ppm/°C end-to-end tempco-making it optimal for compact, battery-powered, thermally demanding systems requiring two independent analog adjustments.
Availability
ISL23425WFVZ-T7A is available at Aetrix Electronics and suitable for power supply margining, sensor trimming, battery-powered instrument gain control, and RF amplifier bias compensation requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for ISL23425WFVZ-T7A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering microcontrollers, analog power, and SoC solutions for automotive, industrial, and IoT applications.
The ISL23425WFVZ-T7A belongs to Renesas' XDCP™ (eXternally Digitally Controlled Potentiometer) family, engineered for high-precision, low-power analog tuning in space-constrained, thermally aggressive environments where mechanical potentiometers fail.
FAQ
What is the resistance tolerance and temperature coefficient of the ISL23425WFVZ-T7A?
The ISL23425WFVZ-T7A has a 10kΩ total resistance with ±2% tolerance and a guaranteed end-to-end temperature coefficient of 125ppm/°C over -40°C to +125°C. This value is specified for the "W" (10kΩ) option per datasheet FN7873 Rev 1.00, page 4. The ratiometric tempco (TCV) is 8ppm/°C at tap position 0x80, ensuring stable voltage division ratios across temperature.
Does the ISL23425WFVZ-T7A retain wiper settings after power cycling?
No, the ISL23425WFVZ-T7A uses volatile wiper registers (WR0 and WR1). Upon power-up, both wipers reset to mid-scale (128 decimal / 0x80), as confirmed in the datasheet's "Principles of Operation" section (page 13). To restore custom positions, the host MCU must reprogram the registers via SPI after each power-on sequence.
Can the ISL23425WFVZ-T7A operate with different voltages on VCC and VLOGIC simultaneously?
Yes-the ISL23425WFVZ-T7A fully supports independent supplies: VCC may range from 1.7V to 5.5V for the analog potentiometer section, while VLOGIC may be as low as 1.2V (up to 5.5V) for the SPI interface. This allows direct connection to 1.2V or 1.8V microcontrollers without level shifters, as explicitly stated in the "Features" and "Recommended Operating Conditions" sections of FN7873.
What happens to the DCP terminals during shutdown mode of the ISL23425WFVZ-T7A?
When the SHDN bit (ACR[6]) is set to 0, the ISL23425WFVZ-T7A forces each DCP into an end-to-end open-circuit state (RH–RL disconnected) and internally connects each wiper (RW0/RW1) to its respective low terminal (RL0/RL1) through a 2kΩ resistor. This isolates the potentiometer from the circuit while preserving wiper register values, as shown in Figure 25 and described on page 13 of FN7873.
Is the ISL23425WFVZ-T7A pin-compatible with other variants in the ISL23425 family?
Yes-the ISL23425WFVZ-T7A shares the identical 14-lead TSSOP pinout with all other "FVZ" suffix variants (e.g., ISL23425TFVZ, ISL23425UFVZ), differing only in total resistance (10kΩ vs. 50kΩ/100kΩ) and marking. Pin mapping, electrical behavior, and SPI protocol are functionally identical across these variants, enabling drop-in replacement where resistance value matches design requirements.
ISL23425WFVZ-T7A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 2
- Number of Taps:
- 256
- Resistance (Ohms):
- 10k
- Interface:
- SPI
- Memory Type:
- Volatile
- Voltage - Supply:
- 1.2V ~ 5.5V, 1.7V ~ 5.5V
- Features:
- -
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- 125ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 14-TSSOP
- Operating Temperature:
- -40°C ~ 125°C
- Resistance - Wiper (Ohms) (Typ):
- 70
ISL23425WFVZ-T7A FAQ
1.How can I place an order for ISL23425WFVZ-T7A through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL23425WFVZ-T7A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL23425WFVZ-T7A reliable?
The price and inventory of ISL23425WFVZ-T7A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL23425WFVZ-T7A is usually 5 days.
3.What payment methods are accepted for ISL23425WFVZ-T7A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL23425WFVZ-T7A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL23425WFVZ-T7A?
ISL23425WFVZ-T7A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL23425WFVZ-T7A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL23425WFVZ-T7A?
For technical support, including ISL23425WFVZ-T7A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL23425WFVZ-T7A requirements.
6.How does Aetrix verify that ISL23425WFVZ-T7A is sourced from the original manufacturer or authorized distributors?
All ISL23425WFVZ-T7A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL23425WFVZ-T7A meets industry standards.
7.What is the process for return or replacement of ISL23425WFVZ-T7A?
All ISL23425WFVZ-T7A units undergo pre-shipment inspection (PSI). If there is an issue with ISL23425WFVZ-T7A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL23425WFVZ-T7A part is unused and in its original packaging.
Return procedure for ISL23425WFVZ-T7A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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