My Inquiry
My Account
Renesas ISL23428TFVZ-T7A
- Part No.:
- ISL23428TFVZ-T7A
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
ISL23428TFVZ-T7A.pdf
- Description:
- IC DGT POT 100KOHM 128TP 14TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,667
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ISL23428TFVZ-T7A from Renesas Electronics (formerly Intersil) is a dual, volatile, 128-tap digitally controlled potentiometer with SPI interface, 100kΩ total resistance, -40°C to +125°C operation, and 14-lead TSSOP package. It functions as two independent programmable resistive dividers in battery-powered instrumentation, power supply margining, and RF bias compensation circuits.
For engineers reviewing the ISL23428TFVZ-T7A datasheet, ISL23428TFVZ-T7A pinout, ISL23428TFVZ-T7A application, or ISL23428TFVZ-T7A equivalent, key selection criteria include its dual-channel 128-tap resolution, independent VCC (1.7–5.5V) and VLOGIC (1.2–5.5V) supplies, 70Ω typical wiper resistance at 3.3V, shutdown mode with end-to-end open circuit, and extended temperature range suitability for automotive and industrial embedded systems.
Technical Context
The ISL23428TFVZ-T7A integrates two monolithic CMOS DCP cores with make-before-break wiper switching, volatile 8-bit Wiper Registers (WR0/WR1), and SPI Mode 0 serial interface operating up to 5MHz (VLOGIC ≥ 1.7V). Each channel supports voltage divider or rheostat configuration with guaranteed monotonicity and ±0.15 LSB INL/DNL over temperature.
Its dual-supply architecture decouples analog (VCC) and digital (VLOGIC) domains, enabling direct interfacing with 1.2V logic without level shifters. Shutdown mode forces RH–RL open-circuit while internally connecting RW to RL via 2kΩ, reducing leakage and isolating the DCP network during system sleep states.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total Resistance | 100kΩ - defines full-scale resistance between RH and RL pins; determines current handling and voltage division ratio in gain/offset circuits. |
| Tap Count | 128 - provides 7-bit resolution (0–127 decimal); enables fine-grained adjustment of analog parameters like sensor bias or amplifier gain. |
| VCC Range | 1.7V to 5.5V - supports wide analog supply range including single-cell Li-ion (3.0–3.7V) and 3.3V/5V systems without external regulators. |
| VLOGIC Range | 1.2V to 5.5V - allows direct connection to ultra-low-voltage microcontrollers (e.g., ARM Cortex-M0+ at 1.2V IO) without level translation. |
| Wiper Resistance | 70Ω typical @ 3.3V - limits insertion error in precision voltage divider applications; impacts THD and noise floor in audio/sensor signal paths. |
| Shutdown Current | 1.2µA @ VCC = VLOGIC = 1.7V - minimizes quiescent power in always-on battery systems; enables >10-year coin-cell operation in low-duty-cycle monitoring nodes. |
| Temperature Range | -40°C to +125°C - qualified for under-hood automotive, industrial motor control, and outdoor telecom equipment without derating. |
Pinout & Package
ISL23428TFVZ-T7A is housed in a RoHS-compliant, 14-lead TSSOP package (M14.173) with 0.65mm pitch and exposed pad for thermal dissipation. Pin numbering follows standard top-view orientation with pin 1 at top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Pins 1, 7) | Ground reference | Dual ground pins reduce ground bounce and improve PSRR in dual-channel operation; must be connected to low-impedance analog ground plane. |
| VLOGIC (Pin 2) | Digital supply input | Provides power to SPI interface and control logic; sets logic threshold levels (VIH/VIL) and enables 1.2V bus compatibility. |
| SDO (Pin 3) | SPI data output | Configurable Push-Pull or Open-Drain output; default Push-Pull eliminates need for external pull-up in most MCU interfaces. |
| SCK (Pin 4) | SPI clock input | Accepts up to 5MHz clock (≥1.7V VLOGIC); rising edge clocks data in, falling edge clocks data out per SPI Mode 0 timing. |
| SDI (Pin 5) | SPI data input | Receives instruction and data bytes; MSB-first protocol requires precise setup/hold timing (50ns @ ≥1.7V). |
| CS (Pin 6) | Chip select input | Active-low enable; falling edge initiates SPI transaction; rising edge triggers wiper settling and shutdown release. |
| RL1 (Pin 8) | DCP1 low terminal | Fixed end of second potentiometer array; connects to reference or signal return path in voltage divider configurations. |
| RW1 (Pin 9) | DCP1 wiper terminal | Movable contact point; position set by WR1 register; delivers adjustable voltage or resistance between RL1 and RH1. |
| RH1 (Pin 10) | DCP1 high terminal | Fixed end of second potentiometer array; typically tied to VCC or bias voltage source in active circuits. |
| RH0 (Pin 11) | DCP0 high terminal | Fixed end of first potentiometer array; used for gain-setting feedback networks or reference voltage scaling. |
| RW0 (Pin 12) | DCP0 wiper terminal | Movable contact point; position set by WR0 register; independently controllable from RW1 for dual-loop calibration. |
| RL0 (Pin 13) | DCP0 low terminal | Fixed end of first potentiometer array; connects to ground or virtual ground in op-amp-based applications. |
| VCC (Pin 14) | Analog supply input | Power for resistor arrays and wiper switches; must remain within 1.7–5.5V and ramp before or simultaneously with VLOGIC. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 128-tap DCPs | Enables simultaneous calibration of two independent analog paths (e.g., differential sensor offset + gain) without board space penalty of discrete pots. |
| Volatile Wiper Registers (WR0/WR1) | Allows dynamic real-time adjustment via SPI; power-on reset to 64 (mid-scale) ensures known startup state for fail-safe systems. |
| Independent VCC/VLOGIC supplies | Eliminates level-shifter ICs when interfacing with sub-1.8V MCUs; reduces BOM count and layout complexity in mixed-voltage designs. |
| Shutdown mode with RW–RL short | Isolates DCP terminals from circuit during sleep; prevents leakage-induced drift in high-impedance sensor nodes and extends battery life. |
| Guaranteed monotonicity & ±0.15 LSB INL | Ensures predictable step response in closed-loop control (e.g., laser diode bias); avoids instability caused by non-monotonic transfer functions. |
| Extended -40°C to +125°C operation | Validated for under-hood automotive ECUs and industrial PLC I/O modules without thermal derating or external heatsinking. |
Applications
| Power Supply Margining | RF Power Amplifier Bias |
|---|---|
|
Use Scenario: Adjusting output voltage of DC-DC converters during production test to verify regulation tolerance across line/load/temperature. IC Role / Device Role / Timing Role: Dual-channel ISL23428TFVZ-T7A replaces mechanical trimpots on feedback dividers of primary and secondary rails, enabling automated calibration via host MCU. Use Value: Achieves ±0.5% voltage accuracy over temperature using 100kΩ channels; eliminates manual tuning labor and improves test throughput by 4×. |
Use Scenario: Compensating temperature-induced drift in GaN HEMT gate bias networks to maintain constant output power and efficiency. IC Role / Device Role / Timing Role: One DCP channel sets fixed bias voltage; the other dynamically adjusts based on temperature sensor feedback to counteract Vgs drift. Use Value: Maintains PA efficiency within ±1.2% over -40°C to +125°C using ratiometric TCV of 2.3ppm/°C (100kΩ option), reducing thermal runaway risk. |
| Sensor Circuit Trimming | Battery-Powered Instrument Gain |
|
Use Scenario: Nulling offset voltage and scaling full-scale output of MEMS pressure sensors in portable medical devices. IC Role / Device Role / Timing Role: ISL23428TFVZ-T7A implements two-point calibration: one channel for zero-offset trim, the other for span adjustment in analog front-end. Use Value: Delivers <±100µV offset error after calibration using 70Ω wiper resistance and 128-step resolution; meets ISO 80601 clinical accuracy requirements. |
Use Scenario: Setting programmable gain in handheld multimeters and oscilloscope front-ends powered by single 3.7V Li-ion cells. IC Role / Device Role / Timing Role: Configured as rheostat between op-amp feedback and inverting input to adjust transimpedance gain without changing PCB layout. Use Value: Supports 100kΩ gain range with <0.05% gain error drift over battery discharge (3.7V → 3.0V) due to matched DCP-to-DCP tracking (±0.5 LSB). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5242BRUZ100 | 100kΩ dual DCP, I²C interface, 16-lead TSSOP, 2.7–5.5V single supply, no VLOGIC independence | Lacks separate VLOGIC rail; requires level shifting for <1.8V MCUs; higher 100µA typical ICC vs 10µA at 1.7V for ISL23428TFVZ-T7A | Select when I²C bus is preferred and system uses only 3.3V/5V logic; avoid for ultra-low-voltage or battery-critical designs. |
| MCP42100-E/ST | 100kΩ dual DCP, SPI interface, 14-lead TSSOP, 2.7–5.5V single supply, no shutdown mode | No dedicated shutdown function; wiper remains electrically connected during sleep; higher 1µA standby current vs 1.2µA shutdown for ISL23428TFVZ-T7A | Choose for cost-sensitive applications where shutdown isolation is unnecessary and 2.7V minimum VCC is acceptable. |
Compared with AD5242BRUZ100 and MCP42100-E/ST, the ISL23428TFVZ-T7A uniquely supports 1.2V logic compatibility and hardware shutdown with RW–RL shorting-critical for energy harvesting and automotive sleep-mode compliance.
Availability
ISL23428TFVZ-T7A is available at Aetrix Electronics and suitable for power supply margining, RF amplifier bias compensation, sensor trimming, battery-powered instrumentation, and industrial temperature monitoring requiring stable component supply across extended temperature ranges.
Supply support for ISL23428TFVZ-T7A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded design innovation through high-performance analog, power, and microcontroller solutions.
The ISL23428TFVZ-T7A belongs to Renesas' XDCP™ (eXtreme Digital Controlled Potentiometer) family, engineered for precision analog trimming in harsh environments where reliability, low power, and mixed-voltage interoperability are critical.
FAQ
What is the total resistance value specified for the ISL23428TFVZ-T7A?
The ISL23428TFVZ-T7A is configured with a nominal total resistance of 100kΩ between each RH and RL terminal pair. This value is confirmed in the Ordering Information table (Page 3 of FN7904 Rev 2.00) and applies across the full -40°C to +125°C operating temperature range with ±20% tolerance. The 100kΩ option is designated by the "T" suffix in the part number family.
Does the ISL23428TFVZ-T7A support independent power supplies for analog and digital sections?
Yes, the ISL23428TFVZ-T7A features separate VCC (1.7–5.5V) and VLOGIC (1.2–5.5V) supply pins. This architecture allows direct interfacing with low-voltage microcontrollers (e.g., 1.2V I/O) without external level shifters, while maintaining full analog performance at higher VCC levels-enabling robust operation in mixed-signal systems.
What happens to the wiper position of the ISL23428TFVZ-T7A during power-up?
Upon power-up, both wiper registers (WR0 and WR1) of the ISL23428TFVZ-T7A automatically reset to 40h (64 decimal), positioning each wiper at mid-scale (tap 64) between RH and RL. This behavior is guaranteed in the datasheet (Page 1) and ensures a known, repeatable startup state for safety-critical calibration sequences.
How does the shutdown mode function in the ISL23428TFVZ-T7A?
In shutdown mode (activated by setting SHDN bit in ACR), the ISL23428TFVZ-T7A forces an open circuit between RH and RL terminals while internally connecting each RW to its corresponding RL via a 2kΩ resistor. This isolates the DCP from the circuit, reduces leakage, and lowers supply current to 1.2µA at 1.7V-verified in the Operating Specifications table (Page 6).
What package type and lead count does the ISL23428TFVZ-T7A use?
The ISL23428TFVZ-T7A is packaged in a 14-lead TSSOP (Thin Shrink Small Outline Package) with RoHS-compliant matte tin plating (e3 termination), as specified in the Ordering Information table (Page 3) and Pin Configurations diagram (Page 2). Its package drawing number is M14.173.
ISL23428TFVZ-T7A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 2
- Number of Taps:
- 128
- Resistance (Ohms):
- 100k
- Interface:
- SPI
- Memory Type:
- Volatile
- Voltage - Supply:
- 1.2V ~ 5.5V, 1.7V ~ 5.5V
- Features:
- -
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- 45ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 14-TSSOP
- Operating Temperature:
- -40°C ~ 125°C
- Resistance - Wiper (Ohms) (Typ):
- 70
ISL23428TFVZ-T7A FAQ
1.How can I place an order for ISL23428TFVZ-T7A through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL23428TFVZ-T7A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL23428TFVZ-T7A reliable?
The price and inventory of ISL23428TFVZ-T7A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL23428TFVZ-T7A is usually 5 days.
3.What payment methods are accepted for ISL23428TFVZ-T7A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL23428TFVZ-T7A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL23428TFVZ-T7A?
ISL23428TFVZ-T7A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL23428TFVZ-T7A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL23428TFVZ-T7A?
For technical support, including ISL23428TFVZ-T7A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL23428TFVZ-T7A requirements.
6.How does Aetrix verify that ISL23428TFVZ-T7A is sourced from the original manufacturer or authorized distributors?
All ISL23428TFVZ-T7A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL23428TFVZ-T7A meets industry standards.
7.What is the process for return or replacement of ISL23428TFVZ-T7A?
All ISL23428TFVZ-T7A units undergo pre-shipment inspection (PSI). If there is an issue with ISL23428TFVZ-T7A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL23428TFVZ-T7A part is unused and in its original packaging.
Return procedure for ISL23428TFVZ-T7A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ISL23428TFVZ-T7A Tags
-
MCP4018T-103E/LT
Microchip Technology
-
MCP4018T-503E/LT
Microchip Technology
-
MCP4011T-103E/SN
Microchip Technology
-
MCP4018T-104E/LT
Microchip Technology
-
MCP4017T-503E/LT
Microchip Technology
-
MCP4018T-502E/LT
Microchip Technology
-
MCP4017T-103E/LT
Microchip Technology
-
MCP4531T-103E/MF
Microchip Technology
-
MCP4021T-202E/SN
Microchip Technology
-
MCP4023T-103E/CH
Microchip Technology
-
MCP4022T-503E/CH
Microchip Technology
-
MCP4551T-502E/MS
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
