Renesas ISL23428UFRUZ-T7A
- Part No.:
- ISL23428UFRUZ-T7A
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 16-UFQFN
- Datasheet:
-
ISL23428UFRUZ-T7A.pdf
- Description:
- IC DGT POT 50KOHM 128TAP 16UTQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL23428UFRUZ-T7A from Renesas (formerly Intersil) is a dual, volatile, 128-tap digitally controlled potentiometer with SPI interface, designed for precision analog trimming in low-voltage systems. It features two independent 50kΩ DCPs, 1.2V–5.5V logic supply (VLOGIC), 1.7V–5.5V analog supply (VCC), and operates across –40°C to +125°C. Used in battery-powered instrumentation for gain adjustment and sensor trimming.
For engineers reviewing the ISL23428UFRUZ-T7A datasheet, ISL23428UFRUZ-T7A pinout, ISL23428UFRUZ-T7A application, or ISL23428UFRUZ-T7A equivalent, key selection criteria include dual-channel 50kΩ resistance, UTQFN-16 package, SPI-compatible 1.2V logic interface, shutdown mode behavior, and wiper settling time under 1.5µs.
Technical Context
The ISL23428UFRUZ-T7A integrates two independent DCP cores on a monolithic CMOS die, each with an 8-bit volatile Wiper Register (WR0/WR1) directly accessible via SPI Mode 0. Wiper positioning uses make-before-break switching, ensuring monotonic resistance transitions between RH, RW, and RL terminals.
Its dual power domains isolate VLOGIC (1.2V–5.5V) from VCC (1.7V–5.5V), enabling direct interfacing with ultra-low-voltage microcontrollers without level shifters. Shutdown mode forces end-to-end open circuit and internally connects RW to RL through a 2kΩ resistor, reducing system leakage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total Resistance | 50kΩ per DCP - defines full-scale voltage divider range and current-handling capability in rheostat mode. |
| Tap Count | 128 taps - provides 7.8mV/LSB resolution at 1V full-scale in voltage divider mode. |
| VLOGIC Range | 1.2V to 5.5V - enables direct connection to 1.2V/1.8V/3.3V/5V logic without external level translation. |
| Wiper Settling Time | 1.5µs (U option) - ensures fast reconfiguration during dynamic calibration sequences. |
| Operating Temp | –40°C to +125°C - supports automotive under-hood, industrial control, and harsh-environment applications. |
| Shutdown Current | ≤1.2µA @ VCC/VLOGIC = 1.7V/1.2V - minimizes quiescent drain in always-on battery systems. |
| Wiper Resistance | 70Ω typical @ 3.3V - limits insertion error and thermal noise in precision signal paths. |
Pinout & Package
ISL23428UFRUZ-T7A is packaged in a 16-lead UTQFN (2.6mm × 1.8mm, 0.5mm pitch), RoHS-compliant, with wettable flank terminations.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Pins 1, 5, 6, 15) | Ground reference | Four dedicated ground pins reduce ground bounce and improve PSRR in dual-channel operation. |
| VLOGIC (Pin 2) | Digital supply input | Power source for SPI interface logic; independent of VCC, enabling mixed-supply system integration. |
| SDO (Pin 3) | SPI data output | Configurable Push-Pull or Open-Drain; tri-stated when CS is high to prevent bus contention. |
| SCK (Pin 4) | SPI clock input | Accepts up to 5MHz clock (≥1.7V VLOGIC); timing-critical for register write/read latency. |
| SDI (Pin 5) | SPI data input | Receives instruction + data bytes on rising SCK edge; supports daisy-chaining multiple DCPs. |
| CS (Pin 6) | Chip select | Active-low enable; must transition low before any SPI transaction; controls standby/shutdown entry. |
| RL1 (Pin 7) | DCP1 low terminal | Fixed end of second potentiometer array; used as reference node in voltage divider or rheostat mode. |
| RW1 (Pin 8) | DCP1 wiper | Movable terminal of second DCP; position set by WR1 register; connects to load or feedback path. |
| RH1 (Pin 9) | DCP1 high terminal | Fixed end of second potentiometer array; typically tied to VCC or bias voltage. |
| RH0 (Pin 10) | DCP0 high terminal | Fixed end of first potentiometer array; shares same voltage domain as RH1 but electrically isolated. |
| RW0 (Pin 11) | DCP0 wiper | Movable terminal of first DCP; independently controllable via WR0; supports dual-loop calibration. |
| RL0 (Pin 12) | DCP0 low terminal | Fixed end of first potentiometer array; may be grounded or biased to define offset. |
| VCC (Pin 13) | Analog supply | Power for resistor array and wiper switches; sets maximum DCP terminal voltage range (0 to VCC). |
| SDO (Pin 14) | SPI data output | Redundant SDO pin for layout flexibility; electrically identical to Pin 3. |
| NC (Pin 7) | No connect | Internally unconnected; must be left floating or tied to GND per PCB design rules. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 50kΩ DCPs | Enables simultaneous trimming of two independent analog paths-e.g., differential amplifier gain and offset-without inter-channel crosstalk. |
| VLOGIC = 1.2V support | Eliminates need for external level shifters when interfacing with 1.2V FPGA I/O banks or ultra-low-power MCUs. |
| Volatile wiper registers | Allows runtime recalibration; wipers reset to mid-scale (64) on power-up, ensuring known startup state. |
| Shutdown mode | Disconnects DCP arrays from circuit while preserving WR values, preventing unintended loading during sleep states. |
| Make-before-break switching | Prevents momentary open circuits during tap transitions-critical for stable feedback loops in closed-loop systems. |
Applications
| Power Supply Margining | Sensor Circuit Trimming |
|---|---|
Use Scenario: Adjusting reference voltage thresholds in PMICs or DC-DC controllers to validate tolerance margins under varying load/temperature. IC Role / Device Role / Timing Role: Dual DCP acts as programmable voltage divider on feedback node; one channel sets nominal output, the other injects controlled offset. Use Value: Enables automated margin testing across production lots without hardware changes-reducing test fixture complexity and cycle time. | Use Scenario: Calibrating offset and gain errors in bridge-based pressure or temperature sensors prior to deployment. IC Role / Device Role / Timing Role: ISL23428UFRUZ-T7A serves as precision trim network in analog front-end; WR0 adjusts zero-point, WR1 scales full-scale response. Use Value: Achieves <±0.1% gain matching across channels using factory-programmed WR values stored in host MCU nonvolatile memory. |
| Battery-Powered Instrument Gain | RF Power Amplifier Bias |
Use Scenario: Dynamically adjusting gain in portable oscilloscopes or handheld multimeters to maintain SNR across input ranges. IC Role / Device Role / Timing Role: Configured as rheostat between op-amp feedback path and ground; WR0/WR1 tuned in real time via SPI during autoranging. Use Value: Delivers 128-step resolution with <1.5µs settling-enabling sub-millisecond range switching without signal disruption. | Use Scenario: Compensating for temperature-induced drift in GaAs FET bias networks within cellular base station RF modules. IC Role / Device Role / Timing Role: Dual DCP sets gate voltage (WR0) and source degeneration (WR1) independently to stabilize Idq over –40°C to +125°C. Use Value: Reduces PA output power variation to ±0.3dB across temperature using ratiometric TCV of 4ppm/°C (U option). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL23428TFRUZ-TK | Same dual 50kΩ DCP, identical UTQFN-16 package, but marked "GBR" and specified for tape-and-reel TK packaging. | Functionally identical; recommended replacement per datasheet Note 1 for ISL23428UFRUZ-T7A due to obsolescence status. | Select when requiring latest production lot with guaranteed long-term availability and updated MSL rating. |
| AD5242BRUZ100 | 100kΩ dual DCP, I²C interface, 2.7V–5.5V single supply, no VLOGIC independence; 14-TSSOP only. | Lacks 1.2V logic compatibility and dual-supply isolation; requires level shifting for sub-1.8V hosts; not suitable for ultra-low-voltage systems. | Choose only if I²C interface and 100kΩ value align with existing BOM and layout constraints-no pin compatibility. |
Compared with ISL23428UFRUZ-T7A, ISL23428TFRUZ-TK offers identical electrical performance and pinout with enhanced supply chain continuity, while AD5242BRUZ100 trades VLOGIC flexibility and low-voltage support for I²C simplicity and higher resistance-requiring redesign for logic interface and supply routing.
Availability
ISL23428UFRUZ-T7A is available at Aetrix Electronics and suitable for power supply margining, sensor circuit trimming, and battery-powered instrument gain adjustment requiring stable component supply across extended temperature ranges and low-voltage logic compatibility.
Supply support for ISL23428UFRUZ-T7A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation acquired Intersil in 2017 and maintains full technical and manufacturing responsibility for the ISL23428 family.
The ISL23428 product line delivers high-precision, low-voltage digital potentiometers for trimming, calibration, and bias control in space-constrained, battery-sensitive, and thermally demanding applications.
FAQ
What is the total resistance value of the ISL23428UFRUZ-T7A?
The ISL23428UFRUZ-T7A has a nominal total resistance of 50kΩ per potentiometer channel (RH0–RL0 and RH1–RL1). This value is confirmed in the Ordering Information table (Page 3) and Analog Specifications (Page 4) of FN7904 Rev 2.00, where "U option" corresponds to 50kΩ. Tolerance is ±2% over temperature.
Does the ISL23428UFRUZ-T7A retain wiper settings after power cycling?
No, the ISL23428UFRUZ-T7A uses volatile wiper registers (WR0 and WR1). Upon power-up, both wipers reset to mid-scale (64 decimal, or 40h), as stated in the Datasheet Section "Principles of Operation" (Page 14). Persistent storage requires external MCU firmware to reload values post-power-on reset.
Can the ISL23428UFRUZ-T7A operate with VLOGIC = 1.2V and VCC = 1.7V simultaneously?
Yes, the ISL23428UFRUZ-T7A fully supports independent 1.2V VLOGIC and 1.7V VCC operation. The datasheet specifies VLOGIC = 1.2V–5.5V and VCC = 1.7V–5.5V across the full temperature range. Standby current drops to 1.2µA under these conditions (Page 6, ICC SB parameter).
What is the function of the SHDN bit in the Access Control Register of the ISL23428UFRUZ-T7A?
The SHDN bit (ACR[6]) enables global shutdown mode for both DCP channels. When set to 0, it forces each DCP into end-to-end open circuit while connecting RWi to RLi via a 2kΩ internal resistor (Figure 25, Page 14). Default state is SHDN = 1 (active). WR values are preserved during shutdown.
Is the ISL23428UFRUZ-T7A pin-compatible with other variants in the ISL23428 family?
Yes, all ISL23428 variants in the 16-lead UTQFN package-including ISL23428UFRUZ-T7A, ISL23428TFRUZ-TK, and ISL23428WFRUZ-T7A-share identical pinout and footprint (L16.2.6x1.8A drawing). Resistance value (10kΩ/50kΩ/100kΩ) and marking differ, but electrical interface and timing are fully compatible.
ISL23428UFRUZ-T7A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 16-UFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 2
- Number of Taps:
- 128
- Resistance (Ohms):
- 50k
- Interface:
- SPI
- Memory Type:
- Volatile
- Voltage - Supply:
- 1.2V ~ 5.5V, 1.7V ~ 5.5V
- Features:
- -
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- 65ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 16-UTQFN (2.6x1.8)
- Operating Temperature:
- -40°C ~ 125°C
- Resistance - Wiper (Ohms) (Typ):
- 70
ISL23428UFRUZ-T7A FAQ
1.How can I place an order for ISL23428UFRUZ-T7A through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL23428UFRUZ-T7A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL23428UFRUZ-T7A reliable?
The price and inventory of ISL23428UFRUZ-T7A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL23428UFRUZ-T7A is usually 5 days.
3.What payment methods are accepted for ISL23428UFRUZ-T7A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL23428UFRUZ-T7A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL23428UFRUZ-T7A?
ISL23428UFRUZ-T7A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL23428UFRUZ-T7A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL23428UFRUZ-T7A?
For technical support, including ISL23428UFRUZ-T7A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL23428UFRUZ-T7A requirements.
6.How does Aetrix verify that ISL23428UFRUZ-T7A is sourced from the original manufacturer or authorized distributors?
All ISL23428UFRUZ-T7A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL23428UFRUZ-T7A meets industry standards.
7.What is the process for return or replacement of ISL23428UFRUZ-T7A?
All ISL23428UFRUZ-T7A units undergo pre-shipment inspection (PSI). If there is an issue with ISL23428UFRUZ-T7A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL23428UFRUZ-T7A part is unused and in its original packaging.
Return procedure for ISL23428UFRUZ-T7A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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